avoid using default tripleusers/arichardson/spr/amdgpu-baseline-test-for-ptrtoaddr-code-generation

Created using spr 1.3.8-beta.1

2 files changed, 23 insertions, 23 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll
index f01173a46e64..e56c99a4316f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -global-isel -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel -verify-machineinstrs < %s | FileCheck %s
 ;; Check that we can lower ptrtoaddr differently from ptrtoint.
 ;; Includes an ignored argument so the registers actually need to be written
 ;; Also all functions are zeroext to show that non-address bits are masked off
@@ -121,8 +121,8 @@ define zeroext i48 @ptrtoaddr_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %p
 ; CHECK-LABEL: ptrtoaddr_as8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
   ret i48 %ret
@@ -151,9 +151,9 @@ define <2 x i64> @ptrtoaddr_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspac
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v2, v8
 ; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v9
-; CHECK-NEXT:    v_mov_b32_e32 v2, v8
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
   %ret = zext <2 x i48> %addr to <2 x i64>
@@ -261,6 +261,7 @@ define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoint_ext_as5_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
@@ -268,7 +269,6 @@ define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoint ptr addrspace(5) %ptr to i256
   ret i256 %ret
@@ -279,6 +279,7 @@ define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoaddr_ext_as5_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
@@ -286,7 +287,6 @@ define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
   %ret = zext i32 %addr to i256
@@ -354,9 +354,9 @@ define <2 x i64> @ptrtoaddr_vec_as8_sgpr(ptr addrspace(8) inreg %ignored, <2 x p
 ; CHECK-LABEL: ptrtoaddr_vec_as8_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, v4
 ; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v1
 ; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v5
-; CHECK-NEXT:    v_mov_b32_e32 v2, v4
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
   %ret = zext <2 x i48> %addr to <2 x i64>
@@ -367,14 +367,14 @@ define zeroext i256 @ptrtoint_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoint_ext_as8_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v4, 0
-; CHECK-NEXT:    v_mov_b32_e32 v5, 0
-; CHECK-NEXT:    v_mov_b32_e32 v6, 0
-; CHECK-NEXT:    v_mov_b32_e32 v7, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s20
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s21
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s22
 ; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoint ptr addrspace(8) %ptr to i256
   ret i256 %ret
@@ -386,14 +386,14 @@ define zeroext i256 @ptrtoaddr_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v4, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s20
-; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
   %ret = zext i48 %addr to i256
diff --git a/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll b/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll
index a5b77846e208..913a5748a6c4 100644
--- a/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
 ;; Check that we can lower ptrtoaddr differently from ptrtoint.
 ;; Includes an ignored argument so the registers actually need to be written
 ;; Also all functions are zeroext to show that non-address bits are masked off
@@ -121,8 +121,8 @@ define zeroext i48 @ptrtoaddr_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %p
 ; CHECK-LABEL: ptrtoaddr_as8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
   ret i48 %ret
@@ -151,9 +151,9 @@ define <2 x i64> @ptrtoaddr_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspac
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v2, v8
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
 ; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
 ; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v9
-; CHECK-NEXT:    v_mov_b32_e32 v0, v4
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
   %ret = zext <2 x i48> %addr to <2 x i64>
@@ -261,6 +261,7 @@ define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoint_ext_as5_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
@@ -268,7 +269,6 @@ define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoint ptr addrspace(5) %ptr to i256
   ret i256 %ret
@@ -279,6 +279,7 @@ define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoaddr_ext_as5_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
@@ -286,7 +287,6 @@ define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s17
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
   %ret = zext i32 %addr to i256
@@ -367,14 +367,14 @@ define zeroext i256 @ptrtoint_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr
 ; CHECK-LABEL: ptrtoint_ext_as8_sgpr:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v4, 0
-; CHECK-NEXT:    v_mov_b32_e32 v5, 0
-; CHECK-NEXT:    v_mov_b32_e32 v6, 0
-; CHECK-NEXT:    v_mov_b32_e32 v7, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s20
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s21
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s22
 ; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %ret = ptrtoint ptr addrspace(8) %ptr to i256
   ret i256 %ret
@@ -386,14 +386,14 @@ define zeroext i256 @ptrtoaddr_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v4, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v6, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v7, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s20
-; CHECK-NEXT:    v_mov_b32_e32 v1, s4
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
   %ret = zext i48 %addr to i256