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authorAmir Ayupov <aaupov@fb.com>2025-05-28 22:30:20 -0700
committerAmir Ayupov <aaupov@fb.com>2025-05-28 22:30:20 -0700
commit1d1046d2589318eacc153f055482655e9f65a421 (patch)
tree60c71322b80e2750ea4307432a4df4b6f3eaeeb9
parentea3c225786a71376ab0758cda8f3716da2469142 (diff)
Created using spr 1.3.4
-rw-r--r--bolt/lib/Profile/DataAggregator.cpp5
-rw-r--r--bolt/lib/Profile/DataReader.cpp44
2 files changed, 26 insertions, 23 deletions
diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp
index 6beb60741406..3749dc24175b 100644
--- a/bolt/lib/Profile/DataAggregator.cpp
+++ b/bolt/lib/Profile/DataAggregator.cpp
@@ -49,6 +49,8 @@ static cl::opt<bool>
cl::desc("aggregate basic samples (without LBR info)"),
cl::cat(AggregatorCategory));
+extern cl::opt<bool> DumpData;
+
static cl::opt<std::string>
ITraceAggregation("itrace",
cl::desc("Generate LBR info with perf itrace argument"),
@@ -586,6 +588,9 @@ void DataAggregator::processProfile(BinaryContext &BC) {
for (auto &MemEvents : NamesToMemEvents)
llvm::stable_sort(MemEvents.second.Data);
+ if (opts::DumpData)
+ dump();
+
// Release intermediate storage.
clear(BranchLBRs);
clear(FallthroughLBRs);
diff --git a/bolt/lib/Profile/DataReader.cpp b/bolt/lib/Profile/DataReader.cpp
index c512394f26a3..e63630c90506 100644
--- a/bolt/lib/Profile/DataReader.cpp
+++ b/bolt/lib/Profile/DataReader.cpp
@@ -29,11 +29,9 @@ namespace opts {
extern cl::OptionCategory BoltCategory;
extern llvm::cl::opt<unsigned> Verbosity;
-static cl::opt<bool>
-DumpData("dump-data",
- cl::desc("dump parsed bolt data for debugging"),
- cl::Hidden,
- cl::cat(BoltCategory));
+cl::opt<bool> DumpData("dump-data",
+ cl::desc("dump parsed bolt data for debugging"),
+ cl::Hidden, cl::cat(BoltCategory));
} // namespace opts
@@ -1353,35 +1351,35 @@ bool DataReader::hasLocalsWithFileName() const {
}
void DataReader::dump() const {
- for (const auto &KV : NamesToBranches) {
- const StringRef Name = KV.first;
- const FuncBranchData &FBD = KV.second;
- Diag << Name << " branches:\n";
- for (const BranchInfo &BI : FBD.Data)
+ for (const auto &[Name, FBD] : NamesToBranches) {
+ Diag << Name << ": " << FBD.Data.size() << " branches:\n";
+ size_t Branches = 0;
+ size_t EntryCount = 1;
+ for (const BranchInfo &BI : FBD.Data) {
Diag << BI.From.Name << " " << BI.From.Offset << " " << BI.To.Name << " "
<< BI.To.Offset << " " << BI.Mispreds << " " << BI.Branches << "\n";
- Diag << Name << " entry points:\n";
- for (const BranchInfo &BI : FBD.EntryData)
+ Branches += BI.Branches;
+ }
+ Diag << Name << ": " << FBD.EntryData.size() << " entry points:\n";
+ for (const BranchInfo &BI : FBD.EntryData) {
Diag << BI.From.Name << " " << BI.From.Offset << " " << BI.To.Name << " "
<< BI.To.Offset << " " << BI.Mispreds << " " << BI.Branches << "\n";
+ EntryCount += BI.Branches;
+ }
+ Diag << Name << " branches/entry: " << 1.0 * Branches / EntryCount << '\n';
}
- for (auto I = EventNames.begin(), E = EventNames.end(); I != E; ++I) {
- StringRef Event = I->getKey();
+ for (StringRef Event : EventNames.keys())
Diag << "Data was collected with event: " << Event << "\n";
- }
- for (const auto &KV : NamesToBasicSamples) {
- const StringRef Name = KV.first;
- const FuncBasicSampleData &FSD = KV.second;
- Diag << Name << " samples:\n";
+
+ for (const auto &[Name, FSD] : NamesToBasicSamples) {
+ Diag << Name << ": " << FSD.Data.size() << " basic samples:\n";
for (const BasicSampleInfo &SI : FSD.Data)
Diag << SI.Loc.Name << " " << SI.Loc.Offset << " " << SI.Hits << "\n";
}
- for (const auto &KV : NamesToMemEvents) {
- const StringRef Name = KV.first;
- const FuncMemData &FMD = KV.second;
- Diag << "Memory events for " << Name;
+ for (const auto &[Name, FMD] : NamesToMemEvents) {
+ Diag << Name << ": " << FMD.Data.size() << " memory events:\n";
Location LastOffset(0);
for (const MemInfo &MI : FMD.Data) {
if (MI.Offset == LastOffset)