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authorBenjamin Maxwell <benjamin.maxwell@arm.com>2025-11-18 14:04:07 +0000
committerBenjamin Maxwell <benjamin.maxwell@arm.com>2025-11-18 14:04:07 +0000
commitf6ab6175362a3a7a1280a53ff55a3a0b72fa7a8f (patch)
tree1e54c8cbbae642115864a41f324f3cfd921cd150
parent6a9d864861e2df2eb3225d2f0129f85fda99bb6c (diff)
Change-Id: I4b5a3d081b7f315e6aec7ce33a6a22194f04d2f4
-rw-r--r--llvm/lib/Target/AArch64/MachineSMEABIPass.cpp7
1 files changed, 2 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index 5b65d734101c..afc004825db6 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -856,15 +856,12 @@ void MachineSMEABI::emitSMEPrologue(MachineBasicBlock &MBB,
.addImm(AArch64SVCR::SVCRZA)
.addImm(1);
} else if (AFI->getSMEFnAttrs().hasSharedZAInterface()) {
- if (ZeroZA) {
+ if (ZeroZA)
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ZERO_M))
.addImm(ZERO_ALL_ZA_MASK)
.addDef(AArch64::ZAB0, RegState::ImplicitDefine);
- }
- if (ZeroZT0) {
- DebugLoc DL = getDebugLoc(MBB, MBBI);
+ if (ZeroZT0)
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ZERO_T)).addDef(AArch64::ZT0);
- }
}
}