llvm-project.git/mlir/test/Target, branch main

[MLIR] Drop use of REQUIRES:shell from tests (#168989)

2025-11-21T17:59:17+00:00

This patch drops two instances of REQUIRES: shell from MLIR tests. This
feature does not mean much given the internal shell is the default for
MLIR. It does prevent these tests from running on Windows, but it does
not seem like there is anything inherent to these tests preventing them
from running on Windows (minus maybe the lack of spirv-tools, which is
explicitly required anyways.

[OpenMP][OMPIRBuilder] Use runtime CC for runtime calls (#168608)

2025-11-21T15:40:20+00:00

Some targets have a specific calling convention that should be used for
generated calls to runtime functions.

Pass that down and use it.

Signed-off-by: Nick Sarnie

[mlir][ROCDL] Adds wmma scaled intrinsics for gfx1250 (#165915)

2025-11-21T15:04:29+00:00

Signed-off-by: Muzammiluddin Syed

[mlir][llvm] Handle debug record import edge cases (#168774)

2025-11-21T07:54:45+00:00

This commit enables the direct import of debug records by default and
fixes issues with two edge cases:
- Detect early on if the address operand is an argument list (calling
getAddress() for argument lists asserts)
- Use getAddress() to check if the address operand is null, which means
the address operand is an empty metadata node, which currently is not
supported.
- Add support for debug label records.

This is a follow-up to:
https://github.com/llvm/llvm-project/pull/167812

[mlir][spirv] Add support for SwitchOp (#168713)

2025-11-20T15:19:10+00:00

The dialect implementation mostly copies the one of `cf.switch`, but
aligns naming to the SPIR-V spec.

[mlir][LLVM] Resync memory effect attribute with LLVM IR (#168568)

2025-11-19T16:56:04+00:00

- Add missing locations, namely 'ErrnoMem', 'TargetMem0', and
'TargetMem1'.

Reland "[MLIR][NVVM] Add tcgen05.mma MLIR Ops (#164356)" (#168638)

2025-11-19T09:21:05+00:00

Reland commit fb829bf11feeb53f815a3abf539e63ec3a23ed3d with additional fixes relating to post-merge CI failure

```
/vol/worker/mlir-nvidia/mlir-nvidia-gcc7/llvm.src/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp: In function ‘constexpr llvm::nvvm::CTAGroupKind getNVVMCtaGroupKind(mlir::NVVM::CTAGroupKind)’:
/vol/worker/mlir-nvidia/mlir-nvidia-gcc7/llvm.src/llvm/include/llvm/Support/ErrorHandling.h:165:36: error: call to non-constexpr function ‘void llvm::llvm_unreachable_internal(const char*, const char*, unsigned int)’
   ::llvm::llvm_unreachable_internal(msg, __FILE__, __LINE__)
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
/vol/worker/mlir-nvidia/mlir-nvidia-gcc7/llvm.src/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp:73:3: note: in expansion of macro ‘llvm_unreachable’
   llvm_unreachable("unsupported cta_group value");
   ^
```

Revert "[MLIR][NVVM] Add tcgen05.mma MLIR Ops" (#168583)

2025-11-18T18:15:37+00:00

Reverts llvm/llvm-project#164356

The bots are broken.

Extend MemoryEffects to Support Target-Specific Memory Locations (#148650)

2025-11-18T11:10:58+00:00

This patch introduces preliminary support for additional memory
locations.
They are: target_mem0 and target_mem1 and they model memory locations
that cannot be represented with existing memory locations.

It was a solution suggested in :
https://discourse.llvm.org/t/rfc-improving-fpmr-handling-for-fp8-intrinsics-in-llvm/86868/6

Currently, these locations are not yet target-specific. The goal is to
enable the compiler to express read/write effects on these resources.

[MLIR][NVVM] Add tcgen05.mma MLIR Ops (#164356)

2025-11-18T11:10:31+00:00

This commit adds support for tgen05.mma family of instructions in the NVVM MLIR dialect and lowers to LLVM Intrinsics. Please refer [PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tcgen05-mma-instructions) for information