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<title>llvm-project.git/mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[mlir][MemRef] Add UB as a dependent dialect and use `ub.poison` for Mem2Reg (#168066)</title>
<updated>2025-11-15T20:46:20+00:00</updated>
<author>
<name>Fabian Mora</name>
<email>fmora.dev@gmail.com</email>
</author>
<published>2025-11-15T20:46:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f5b73760e1c4d5d82c02c871b461d665861761fb'/>
<id>f5b73760e1c4d5d82c02c871b461d665861761fb</id>
<content type='text'>
This patch adds `ub` as a dependent dialect to `memref`, and uses
`ub.poison` as the default value in `AllocaOp::getDefaultValue` for the
mem2reg pass.

This aligns the behavior of `mem2reg` with LLVM, where loading a value
before having a value should be poison.

---------

Signed-off-by: Fabian Mora &lt;fabian.mora-cordero@amd.com&gt;</content>
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<pre>
This patch adds `ub` as a dependent dialect to `memref`, and uses
`ub.poison` as the default value in `AllocaOp::getDefaultValue` for the
mem2reg pass.

This aligns the behavior of `mem2reg` with LLVM, where loading a value
before having a value should be poison.

---------

Signed-off-by: Fabian Mora &lt;fabian.mora-cordero@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[mlir][NFC] update `mlir/Dialect` create APIs (18/n) (#149925)</title>
<updated>2025-07-24T20:38:30+00:00</updated>
<author>
<name>Maksim Levental</name>
<email>maksim.levental@gmail.com</email>
</author>
<published>2025-07-24T20:38:30+00:00</published>
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<id>a636b7bfdd1d8304b78e8b42ec900a21736d4afb</id>
<content type='text'>
See https://github.com/llvm/llvm-project/pull/147168 for more info.</content>
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<pre>
See https://github.com/llvm/llvm-project/pull/147168 for more info.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Remove unused includes (NFC) (#148342)</title>
<updated>2025-07-12T18:28:55+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-07-12T18:28:55+00:00</published>
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<id>d5def016b6ee3dcf4e1848ba39aba07e80714b75</id>
<content type='text'>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</content>
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<pre>
These are identified by misc-include-cleaner.  I've filtered out those
that break builds.  Also, I'm staying away from llvm-config.h,
config.h, and Compiler.h, which likely cause platform- or
compiler-specific build failures.</pre>
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</content>
</entry>
<entry>
<title>mlir/LogicalResult: move into llvm (#97309)</title>
<updated>2024-07-02T09:42:33+00:00</updated>
<author>
<name>Ramkumar Ramachandra</name>
<email>ramkumar.ramachandra@codasip.com</email>
</author>
<published>2024-07-02T09:42:33+00:00</published>
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<id>db791b278a414fb6df1acc1799adcf11d8fb9169</id>
<content type='text'>
This patch is part of a project to move the Presburger library into
LLVM.</content>
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<pre>
This patch is part of a project to move the Presburger library into
LLVM.</pre>
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</content>
</entry>
<entry>
<title>[mlir][sroa] Update name of subelement types in destructurable slots (#97226)</title>
<updated>2024-06-30T18:24:56+00:00</updated>
<author>
<name>Théo Degioanni</name>
<email>theo.degioanni.llvm.deluge062@simplelogin.fr</email>
</author>
<published>2024-06-30T18:24:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=69d3793ffbaccc134119d93831199fcc4294579b'/>
<id>69d3793ffbaccc134119d93831199fcc4294579b</id>
<content type='text'>
The `elementPtrs` has changed meaning over time and the name is now
outdated which may be confusing. This PR updates it to a name
representative of current usage.</content>
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<pre>
The `elementPtrs` has changed meaning over time and the name is now
outdated which may be confusing. This PR updates it to a name
representative of current usage.</pre>
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</content>
</entry>
<entry>
<title>[MLIR][SROA] Reuse allocators to avoid rewalking the IR (#91971)</title>
<updated>2024-05-14T08:26:27+00:00</updated>
<author>
<name>Christian Ulmann</name>
<email>christianulmann@gmail.com</email>
</author>
<published>2024-05-14T08:26:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0b5b2027f94c60c73d6871cf64d3f580c27c5a53'/>
<id>0b5b2027f94c60c73d6871cf64d3f580c27c5a53</id>
<content type='text'>
This commit extends the SROA interfaces to ensure the interface
instantiations can communicate newly created allocators to the
algorithm. This ensures that the SROA implementation does no longer
require re-walking the IR to find new allocators.</content>
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<pre>
This commit extends the SROA interfaces to ensure the interface
instantiations can communicate newly created allocators to the
algorithm. This ensures that the SROA implementation does no longer
require re-walking the IR to find new allocators.</pre>
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</content>
</entry>
<entry>
<title>[MLIR][Mem2Reg] Fix multi slot handling &amp; move retry handling (#91464)</title>
<updated>2024-05-13T05:37:41+00:00</updated>
<author>
<name>Christian Ulmann</name>
<email>christianulmann@gmail.com</email>
</author>
<published>2024-05-13T05:37:41+00:00</published>
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<id>eeafc9daa15d2d022bcdd456d4b8bafd23f5f121</id>
<content type='text'>
This commit fixes Mem2Regs mutli-slot allocator handling and extends the
test dialect to test this.

Additionally, this modifies Mem2Reg's API to always attempt a full
promotion on all the passed in "allocators". This ensures that the pass
does not require unnecessary walks over the regions and improves caching
benefits.</content>
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<pre>
This commit fixes Mem2Regs mutli-slot allocator handling and extends the
test dialect to test this.

Additionally, this modifies Mem2Reg's API to always attempt a full
promotion on all the passed in "allocators". This ensures that the pass
does not require unnecessary walks over the regions and improves caching
benefits.</pre>
</div>
</content>
</entry>
<entry>
<title>[MLIR][Interfaces] Change MemorySlotInterface to use OpBuilder (#91341)</title>
<updated>2024-05-08T05:40:15+00:00</updated>
<author>
<name>Christian Ulmann</name>
<email>christianulmann@gmail.com</email>
</author>
<published>2024-05-08T05:40:15+00:00</published>
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<id>084e2b53d22c11e013b0a495b65d39aa7f934048</id>
<content type='text'>
This commit changes the `MemorySlotInterface` back to using `OpBuilder`
instead of a rewriter. This was originally introduced in
https://reviews.llvm.org/D150432 but it was shown that patterns are a
bad idea for both Mem2Reg and SROA.
Mem2Reg suffers from the usage of a rewriter due to being forced to
create new basic blocks. This is an issue, as it leads to the
invalidation of the dominance information, which can be expensive to
recompute.</content>
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<pre>
This commit changes the `MemorySlotInterface` back to using `OpBuilder`
instead of a rewriter. This was originally introduced in
https://reviews.llvm.org/D150432 but it was shown that patterns are a
bad idea for both Mem2Reg and SROA.
Mem2Reg suffers from the usage of a rewriter due to being forced to
create new basic blocks. This is an issue, as it leads to the
invalidation of the dominance information, which can be expensive to
recompute.</pre>
</div>
</content>
</entry>
<entry>
<title>[MLIR][LLVM][Mem2Reg] Extends support for partial stores (#89740)</title>
<updated>2024-04-24T12:28:15+00:00</updated>
<author>
<name>Christian Ulmann</name>
<email>christianulmann@gmail.com</email>
</author>
<published>2024-04-24T12:28:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6e9ea6ea6897561a9c3bd77b0b93e415fdc7eeb3'/>
<id>6e9ea6ea6897561a9c3bd77b0b93e415fdc7eeb3</id>
<content type='text'>
This commit enhances the LLVM dialect's Mem2Reg interfaces to support
partial stores to memory slots. To achieve this support, the `getStored`
interface method has to be extended with a parameter of the reaching
definition, which is now necessary to produce the resulting value after
this store.</content>
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<pre>
This commit enhances the LLVM dialect's Mem2Reg interfaces to support
partial stores to memory slots. To achieve this support, the `getStored`
interface method has to be extended with a parameter of the reaching
definition, which is now necessary to produce the resulting value after
this store.</pre>
</div>
</content>
</entry>
<entry>
<title>[MLIR][Mem2Reg][LLVM] Enhance partial load support (#89094)</title>
<updated>2024-04-18T11:09:16+00:00</updated>
<author>
<name>Christian Ulmann</name>
<email>christianulmann@gmail.com</email>
</author>
<published>2024-04-18T11:09:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ac39fa740b067f6197dca1caecc97c0da91ebf3d'/>
<id>ac39fa740b067f6197dca1caecc97c0da91ebf3d</id>
<content type='text'>
This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.

Note: There will be additional followups that introduce a similar
functionality for stores, and there are plans to support accesses into
the middle of memory slots.</content>
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<pre>
This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.

Note: There will be additional followups that introduce a similar
functionality for stores, and there are plans to support accesses into
the middle of memory slots.</pre>
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</content>
</entry>
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