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<title>llvm-project.git/llvm/utils/TableGen/X86MnemonicTables.cpp, branch users/nico/python-1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[LLVM][TableGen] Change X86MnemonicTables to use const RecordKeeper (#109053)</title>
<updated>2024-09-18T16:57:31+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2024-09-18T16:57:31+00:00</published>
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<id>74335fb7ae7731a57a163524aeffd93911b50a46</id>
<content type='text'>
Change X86MnemonicTables to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089</content>
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<pre>
Change X86MnemonicTables to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089</pre>
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</content>
</entry>
<entry>
<title>[RFC][TableGen] Restructure TableGen Source (#80847)</title>
<updated>2024-03-25T08:40:35+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2024-03-25T08:40:35+00:00</published>
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<id>fa3d789df15bd1f58fb8ba4ea3be909218cf7f03</id>
<content type='text'>
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)

Fixes #80647</content>
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<pre>
Refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build
`llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen
backends. Such helpers can be shared by more than one backend, and even
unit tested (e.g. CodeExpander is, maybe we can add more over time)

Fixes #80647</pre>
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</content>
</entry>
<entry>
<title>llvm-tblgen: Rewrite emitters to use `TableGen::Emitter`</title>
<updated>2023-03-21T07:21:27+00:00</updated>
<author>
<name>NAKAMURA Takumi</name>
<email>geek4civic@gmail.com</email>
</author>
<published>2023-02-19T05:30:14+00:00</published>
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<id>9c93e728bfb8079c1de51e5481168c4083038c2a</id>
<content type='text'>
Each emitter became self-contained since it has the registration of option.

Differential Revision: https://reviews.llvm.org/D144351
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<pre>
Each emitter became self-contained since it has the registration of option.

Differential Revision: https://reviews.llvm.org/D144351
</pre>
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</content>
</entry>
<entry>
<title>llvm-tblgen: Add "TableGenBackends.h" to each emitter.</title>
<updated>2023-02-18T18:06:32+00:00</updated>
<author>
<name>NAKAMURA Takumi</name>
<email>geek4civic@gmail.com</email>
</author>
<published>2023-02-18T17:52:39+00:00</published>
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<id>aeafcbcd75f2338cacfb2d2c2a538a6e3b6a38e7</id>
<content type='text'>
"TableGenBackends.h" has declarations of emitters.
</content>
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<pre>
"TableGenBackends.h" has declarations of emitters.
</pre>
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</entry>
<entry>
<title>llvm-tblgen: Apply IWYU partially</title>
<updated>2023-02-16T15:32:46+00:00</updated>
<author>
<name>NAKAMURA Takumi</name>
<email>geek4civic@gmail.com</email>
</author>
<published>2023-02-16T15:28:07+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[X86][tablgen] Refine the class RecognizableInstr. NFCI</title>
<updated>2022-03-26T14:41:49+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2022-03-26T14:29:23+00:00</published>
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<id>271e8d2495e2194c25cb786b84ab86d15184aac3</id>
<content type='text'>
1. Add comments to explain why we set `isAsmParserOnly` for XACQUIRE and XRELEASE
2. Check `X86Inst` in the constructor of `RecognizableInstrBase` so that
   we can avoid the case where one of it's field is not initialized but
   accessed by user. (e.g. in X86EVEX2VEXTablesEmitter.cpp)
3. Move `Rec` from `RecognizableInstrBase` to `RecognizableInstr` to reduce
   size of `RecognizableInstrBase`
4. Remove out-of-date comments for shouldBeEmitted() (filter() was removed)
5. Add a basic field `IsAsmParserOnly` and remove the field
   `ShouldBeEmitted` b/c we can deduce it w/ little overhead
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<pre>
1. Add comments to explain why we set `isAsmParserOnly` for XACQUIRE and XRELEASE
2. Check `X86Inst` in the constructor of `RecognizableInstrBase` so that
   we can avoid the case where one of it's field is not initialized but
   accessed by user. (e.g. in X86EVEX2VEXTablesEmitter.cpp)
3. Move `Rec` from `RecognizableInstrBase` to `RecognizableInstr` to reduce
   size of `RecognizableInstrBase`
4. Remove out-of-date comments for shouldBeEmitted() (filter() was removed)
5. Add a basic field `IsAsmParserOnly` and remove the field
   `ShouldBeEmitted` b/c we can deduce it w/ little overhead
</pre>
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</entry>
<entry>
<title>[X86][tablgen] Add class RecognizableInstrBase to simplify X86 code, NFCI</title>
<updated>2022-03-26T05:03:06+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2022-03-26T05:00:53+00:00</published>
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<id>bf11ed293abf4dcb2bcd37be3a027a786132e695</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[X86][tablgen] Add interface getMnemonic to namespace X86Disassembler, NFCI</title>
<updated>2022-03-26T01:55:54+00:00</updated>
<author>
<name>Shengchen Kan</name>
<email>shengchen.kan@intel.com</email>
</author>
<published>2022-03-25T12:54:19+00:00</published>
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<id>e13faa40cf0a727a76e395ab4123b9d2ca527b49</id>
<content type='text'>
Address comments in D122477 b/c `getMnemonic` is common to X86 and may be
used in more than one place.
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<pre>
Address comments in D122477 b/c `getMnemonic` is common to X86 and may be
used in more than one place.
</pre>
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</content>
</entry>
<entry>
<title>[X86][NFC] MnemonicTables: only access RI fields if they're initialized</title>
<updated>2022-03-21T16:25:29+00:00</updated>
<author>
<name>Amir Ayupov</name>
<email>aaupov@fb.com</email>
</author>
<published>2022-03-21T14:43:08+00:00</published>
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<id>442e9e1389b51ffb7abd8f59858d92954e53aa90</id>
<content type='text'>
Fix an issue reported by UBSan.

Test Plan:
Configure with `-DLLVM_USE_SANITIZER="Address;Undefined"`
`ninja llc`

Differential Revision: https://reviews.llvm.org/D122140
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<pre>
Fix an issue reported by UBSan.

Test Plan:
Configure with `-DLLVM_USE_SANITIZER="Address;Undefined"`
`ninja llc`

Differential Revision: https://reviews.llvm.org/D122140
</pre>
</div>
</content>
</entry>
<entry>
<title>[TableGen] X86 mnemonic tables backend</title>
<updated>2022-03-18T08:43:53+00:00</updated>
<author>
<name>Amir Ayupov</name>
<email>aaupov@fb.com</email>
</author>
<published>2022-03-18T08:41:10+00:00</published>
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<id>fdcb256f9796de1393763a66c3b38a5859fb6b70</id>
<content type='text'>
Add tablegen backend that generates X86 mnemonic-based opcode groupings, e.g.
`isADD`, `isTEST`, etc.

Addresses https://lists.llvm.org/pipermail/llvm-dev/2022-January/154526.html

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D121571
</content>
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<pre>
Add tablegen backend that generates X86 mnemonic-based opcode groupings, e.g.
`isADD`, `isTEST`, etc.

Addresses https://lists.llvm.org/pipermail/llvm-dev/2022-January/154526.html

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D121571
</pre>
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