llvm-project.git/llvm/utils/TableGen/X86InstrMappingEmitter.cpp, branch users/nico/python-2

[X86][NF] Switch the order of Inst and &Target.getInstruction(NewRec) (#130739)

2025-03-12T09:35:54+00:00

Because Inst is ordered by Instruction ID.

[TableGen] Avoid repeated hash lookups (NFC) (#126344)

2025-02-08T08:48:30+00:00

[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)

2025-01-16T13:20:41+00:00

Also use brace initialization and emplace to avoid explicitly 
constructing std::pair, and the same for std::tuple.

[LLVM][TableGen] Change all `Init` pointers to const (#112705)

2024-10-18T14:50:22+00:00

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

[LLVM][TableGen] Change a few emitters to use const Record pointers (#110112)

2024-09-27T14:07:16+00:00

Change DirectiveEmitter, Option Emitter, and X86 Emitters to use const
Record pointers.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

[LLVM][TableGen] Change X86InstrMapping to use const RecordKeeper (#109066)

2024-09-18T17:41:21+00:00

Change X86InstrMappingEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858)

2024-09-09T21:33:21+00:00

Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to
const pointer.

This is a part of effort to have better const correctness in TableGen
backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089

[X86][AVX10.2] Support AVX10.2 VNNI FP16/INT8/INT16 new instructions (#101783)

2024-08-05T10:57:42+00:00

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965

[X86][MC,Driver] Support -msse2avx to encode SSE instruction with VEX prefix (#96860)

2024-07-16T01:40:45+00:00

For GCC compatibility
https://gcc.gnu.org/onlinedocs/gcc-14.1.0/gcc/x86-Options.html.

[X86][CodeGen] Share code between CompressEVEX pass and ND2NonND transform, NFCI

2024-06-19T08:03:57+00:00