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<title>llvm-project.git/llvm/utils/TableGen/X86DisassemblerTables.cpp, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[TableGen] Use range-based for loops (NFC) (#144283)</title>
<updated>2025-06-16T04:00:29+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-06-16T04:00:29+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[TableGen] Use llvm::append_range (NFC) (#133649)</title>
<updated>2025-03-30T19:21:38+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-03-30T19:21:38+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[TableGen] Use std::pair instead of std::make_pair. NFC. (#123174)</title>
<updated>2025-01-16T13:20:41+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-01-16T13:20:41+00:00</published>
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<content type='text'>
Also use brace initialization and emplace to avoid explicitly 
constructing std::pair, and the same for std::tuple.</content>
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<pre>
Also use brace initialization and emplace to avoid explicitly 
constructing std::pair, and the same for std::tuple.</pre>
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</content>
</entry>
<entry>
<title>[X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)</title>
<updated>2024-08-29T10:22:26+00:00</updated>
<author>
<name>Freddy Ye</name>
<email>freddy.ye@intel.com</email>
</author>
<published>2024-08-29T10:22:26+00:00</published>
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In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.</content>
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<pre>
In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][AVX10.2] Support YMM rounding new instructions (#101825)</title>
<updated>2024-08-04T13:05:45+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-04T13:05:45+00:00</published>
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<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
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<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
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</content>
</entry>
<entry>
<title>Reland "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)" (#101616)</title>
<updated>2024-08-03T01:26:07+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-03T01:26:07+00:00</published>
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<id>259ca9ee9c4d9f7ba2d05db9fe05f782a865aeb5</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
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<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
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</entry>
<entry>
<title>Revert "[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions" (#101612)</title>
<updated>2024-08-02T05:04:10+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-02T05:04:10+00:00</published>
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<id>2e0588d5e1c9e9a0936846173dbc488f462a6c2d</id>
<content type='text'>
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.</content>
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<pre>
Reverts llvm/llvm-project#101452

There are several buildbot failed. Revert first.</pre>
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</content>
</entry>
<entry>
<title>[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)</title>
<updated>2024-08-02T04:10:50+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-08-02T04:10:50+00:00</published>
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<id>10bad2c8d7be1bbb726c536dd306da3cae2247b4</id>
<content type='text'>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</content>
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<pre>
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965</pre>
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</content>
</entry>
<entry>
<title>[llvm] Avoid 'raw_string_ostream::str' (NFC)</title>
<updated>2024-07-05T22:22:03+00:00</updated>
<author>
<name>Youngsuk Kim</name>
<email>youngsuk.kim@hpe.com</email>
</author>
<published>2024-07-05T21:36:19+00:00</published>
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<content type='text'>
Since `raw_string_ostream` doesn't own the string buffer, it is
desirable (in terms of memory safety) for users to directly reference
the string buffer rather than use `raw_string_ostream::str()`.

Work towards TODO item to remove `raw_string_ostream::str()`.
</content>
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<pre>
Since `raw_string_ostream` doesn't own the string buffer, it is
desirable (in terms of memory safety) for users to directly reference
the string buffer rather than use `raw_string_ostream::str()`.

Work towards TODO item to remove `raw_string_ostream::str()`.
</pre>
</div>
</content>
</entry>
<entry>
<title>[X86][MC] Teach disassembler to recognize apx instructions which ignores W bit (#82747)</title>
<updated>2024-02-29T03:44:41+00:00</updated>
<author>
<name>XinWang10</name>
<email>108658776+XinWang10@users.noreply.github.com</email>
</author>
<published>2024-02-29T03:44:41+00:00</published>
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<id>ffa48f0c945be3c1680b0830d5c0cac146cb954c</id>
<content type='text'>
Extended VMX instructions and 8 bit apx extended instructions don't need
W bit, they are marked as W ignored in spec.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</content>
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<pre>
Extended VMX instructions and 8 bit apx extended instructions don't need
W bit, they are marked as W ignored in spec.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4</pre>
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