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<title>llvm-project.git/llvm/utils/TableGen/RegisterInfoEmitter.cpp, branch users/pcc/spr/elf-add-preferred-function-alignment-flag</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[TableGen] Add a bitvector of members of CodeGenRegisterClass (#149122)</title>
<updated>2025-07-16T19:31:32+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-07-16T19:31:32+00:00</published>
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<content type='text'>
This makes CodeGenRegisterClass::contains fast. Use this to simplify
inferMatchingSuperRegClass.</content>
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<pre>
This makes CodeGenRegisterClass::contains fast. Use this to simplify
inferMatchingSuperRegClass.</pre>
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</content>
</entry>
<entry>
<title>[TableGen] Use range-based for loops (NFC) (#144283)</title>
<updated>2025-06-16T04:00:29+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-06-16T04:00:29+00:00</published>
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</pre>
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</entry>
<entry>
<title>[X86][BreakFalseDeps] Using reverse order for undef register selection (#137569)</title>
<updated>2025-06-11T14:08:20+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2025-06-11T14:08:20+00:00</published>
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<content type='text'>
BreakFalseDeps picks the best register for undef operands if
instructions have false dependency. The problem is if the instruction is
close to the beginning of the function, ReachingDefAnalysis is over
optimism to the unused registers, which results in collision with
registers just defined in the caller.

This patch changes the selection of undef register in an reverse order,
which reduces the probability of register collisions between caller and
callee. It brings improvement in some of our internal benchmarks with
negligible effect on other benchmarks.</content>
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<pre>
BreakFalseDeps picks the best register for undef operands if
instructions have false dependency. The problem is if the instruction is
close to the beginning of the function, ReachingDefAnalysis is over
optimism to the unused registers, which results in collision with
registers just defined in the caller.

This patch changes the selection of undef register in an reverse order,
which reduces the probability of register collisions between caller and
callee. It brings improvement in some of our internal benchmarks with
negligible effect on other benchmarks.</pre>
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</content>
</entry>
<entry>
<title>[TableGen][CodeGen] Give every leaf register a unique regunit (#139526)</title>
<updated>2025-05-13T09:52:36+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-05-13T09:52:36+00:00</published>
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<id>28b7d6621a70799705b04d2e08dc98a185151d3a</id>
<content type='text'>
Give every leaf register a unique regunit, even if it has ad hoc
aliases.

Previously only leaf registers *without* ad hoc aliases would get a
unique regunit, but that caused situations where regunits could not be
used to distinguish a register from its subregs. For example:

- Registers A and B alias. They both get regunit 0 only.
- Register C has subregs A and B. It inherits regunits from its subregs,
  so it also gets regunit 0 only.

After this fix, registers A and B will get a unique regunit in addition
to the regunit representing the alias, for example:

- A will get regunits 0 and 1.
- B will get regunits 0 and 2.
- C will get regunits 0, 1 and 2.</content>
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Give every leaf register a unique regunit, even if it has ad hoc
aliases.

Previously only leaf registers *without* ad hoc aliases would get a
unique regunit, but that caused situations where regunits could not be
used to distinguish a register from its subregs. For example:

- Registers A and B alias. They both get regunit 0 only.
- Register C has subregs A and B. It inherits regunits from its subregs,
  so it also gets regunit 0 only.

After this fix, registers A and B will get a unique regunit in addition
to the regunit representing the alias, for example:

- A will get regunits 0 and 1.
- B will get regunits 0 and 2.
- C will get regunits 0, 1 and 2.</pre>
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</content>
</entry>
<entry>
<title>[NFC][TableGen] Use StringRef::str() instead of casting (#139332)</title>
<updated>2025-05-12T22:41:27+00:00</updated>
<author>
<name>Rahul Joshi</name>
<email>rjoshi@nvidia.com</email>
</author>
<published>2025-05-12T22:41:27+00:00</published>
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<id>9981afc5f9d1bb84e35d562f2a1d0f6bf56fcb58</id>
<content type='text'>
- Also eliminate unneeded std::string() around some literal strings.</content>
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- Also eliminate unneeded std::string() around some literal strings.</pre>
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</content>
</entry>
<entry>
<title>[llvm] Use llvm::append_range (NFC) (#135931)</title>
<updated>2025-04-16T19:28:47+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2025-04-16T19:28:47+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[NFC]Make file-local cl::opt global variables static (#126486)</title>
<updated>2025-03-03T06:46:33+00:00</updated>
<author>
<name>chrisPyr</name>
<email>32153107+chrisPyr@users.noreply.github.com</email>
</author>
<published>2025-03-03T06:46:33+00:00</published>
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<id>71f4c7dabec0f32b2d475e8e08f0da99628a067c</id>
<content type='text'>
#125983</content>
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#125983</pre>
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</content>
</entry>
<entry>
<title>TableGen: Generate reverseComposeSubRegIndices (#127050)</title>
<updated>2025-02-17T15:11:26+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-02-17T15:11:26+00:00</published>
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<id>ab2d330feab3e1d9927a3c0de1a9d6e9bda5abe9</id>
<content type='text'>
This is necessary to enable composing subregisters in peephole-opt.
For now use a brute force table to find the return value. The worst
case target is AMDGPU with a 399 x 399 entry table.</content>
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This is necessary to enable composing subregisters in peephole-opt.
For now use a brute force table to find the return value. The worst
case target is AMDGPU with a 399 x 399 entry table.</pre>
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</content>
</entry>
<entry>
<title>TableGen: Add missing consts to CodeGenSubRegIndex</title>
<updated>2025-02-13T09:49:24+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-02-13T08:00:07+00:00</published>
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</pre>
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</entry>
<entry>
<title>[TableGen] Use MCRegister::id() to avoid an implicit conversion from MCRegister to unsigned. NFC</title>
<updated>2025-01-29T07:41:13+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-01-29T07:41:05+00:00</published>
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