Inferring super-register classes naively requires checking every register class against every other register class and sub-register index. Each of those checks is itself a non-trivial operation on register sets. Culling as many (RC, RC, SubIdx) triples as possible is important for the running time of TableGen for architectures with complex sub-register relations. Use transitivity to cull many (RC, RC, SubIdx) triples. This unfortunately requires us to complete the transitive closure of super-register classes explicitly, but it still cuts down the running time on AMDGPU substantially -- in some upcoming work in the backend by more than half (in very rough measurements). This changes the names of some of the inferred register classes, since the order in which they are inferred changes. The names of the inferred register classes become shorter, which reduces the size of the generated files. Replacing some uses of SmallPtrSet by DenseSet shaves off a few more percent; there are hundreds of register classes in AMDGPU. Tweaking the topological signature check to skip reigsters without super-registers further helps skip register classes that have "pseudo" registers in them whose sub- and super-register structure is trivial.
Factor out the timer related functionality from `RecordKeeper` to a new `TGTimer` class in a new file.
Change RegisterBankEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
Generating the mapping from a register class to a register bank is complex: - there can be lots of register classes - the mapping may be ambiguos - a register class can span several register banks (e.g. a register class containing all registers) - the type information is not enough to decide which register bank to map to (e.g. a register class containing floating point and vector registers, and all register can represent a f64 value) The approach taken here is to encode the register banks in an array indexed by the ID of the register class. To save space, the entries are packed into chunks of size 2^n.
Refactor of the llvm-tblgen source into: - a "Basic" library, which contains the bare minimum utilities to build `llvm-min-tablegen` - a "Common" library which contains all of the helpers for TableGen backends. Such helpers can be shared by more than one backend, and even unit tested (e.g. CodeExpander is, maybe we can add more over time) Fixes #80647
``` find llvm/utils/TableGen -iname "*.h" -o -iname "*.cpp" | xargs clang-format-16 -i ``` Split from #80847
RegBanks are constructed as global objects. Making the constructor
constexpr helps the compiler construct it without a global
constructor.
clang's optimizer seems to figure this out on its own, but at
least gcc 8 does not.
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D156110
This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the target. Individual RegisterBanks cannot be constructed with HwMode information as construction is generated by TableGen, but a RegisterBankInfo subclass can provide the HwMode as a constructor argument. The HwMode is used to select the appropriate RegisterBank size from an array relating sizes to RegisterBanks. Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed). Reviewed By: simoncook, craig.topper Differential Revision: https://reviews.llvm.org/D76007