Previously we had one loop over the DAG for immediates and registers and
another loop over the destination operands for mapping from the source.

Now we have a single loop over the destination operands that handles immediates,
registers, and named operands. A helper method is added so we can handle
operands and sub-operands specified by a sub-dag.

My goal is to allow a named operand to appear in a sub-dag which wasn't
supported before. This will allow the destination instruction to have an
operand with sub-operands when the source does not have sub operands.

For RISC-V, I'm looking into using an operand with sub-operands to
represent an reg+offset memory address. I need to be able to lower a
pseudo instruction that only has a register operand to an instruction
that has a reg+offset operand. The offset will be filled in with 0
during expansion and the register will be copied from the source.

The expansion would look like this:
def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                [(riscv_call GPRJALR:$rs1)]>,
PseudoInstExpansion<(JALR X1, (ops GPR:$rs1, 0))>;

Previously we stored the index into the source CodeGenInstruction's
operand list. Any operand with sub operands stored the same index into
all of the OperandMap entries for that operand. The emitting loop would
look up the MIOperandNo for the source and add the sub index.

This patch moves the logic into the loop that updates the OperandMap.
Now the emitting loop only needs to print the value.

While there, I've added a check that MIOperandNo is the same for source
and destination.

All of the notes using the location of ResultInst will just print the
location inside of the PseudoInstExpansion class.

There was one note using the location of DI->getDef(), but knowing where
one of the two mismatched types is defined isn't helpful. The operand
types need to be the same, so the mismatch message we already printed
should be enough.

The code was using the number of source operands plus one. The plus one
seems to be an ARM specific value accounting for one of the source
operands having 2 sub operands. No other target in tree uses
PseudoLowering with variadic instructions so this worked.

This patch replaces it with a proper count of the number of sub operands
of all operands. While there I update the loop to use MIOperandNo so we
don't need to count up the sub operands as we go.

The message looks correct to me.

split PR as requested from
https://github.com/llvm/llvm-project/pull/113318.

Removes unused imports in TableGen BE

Factor out the timer related functionality from `RecordKeeper` to a new
`TGTimer` class in a new file.

Change PseudoLoweringEmitter to use const RecordKeeper.

This is a part of effort to have better const correctness in TableGen backends:


https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089