The Transactional Memory Extension (TME) was introduced as part of
Armv9-A but has not been adopted by the ecosystem. This mirrors what
Arm has observed with similar extensions in other architectures.

Therefore, remove FEAT_TME assembly and ACLE code from llvm, because
support for TME has now been officially withdrawn, as noted here:

```
   FEAT_TME is withdrawn from all future versions of Arm®
   Architecture Reference Manual for A-profile architecture.
```

referenced in Known Issue D24093, documented here:
   https://developer.arm.com/documentation/102105/lb-05/

Add assembly/disassembly support for AArch64 `FEAT_S1POE2` (Stage 1
Permission Overlay Extension 2), as blogged about here:

* https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/future-architecture-technologies-poe2-and-vmte

and as documented here:

* https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies

Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>

Add the following `FEAT_MOPS_GO` instructions:
  * `SETGOP`, `SETGOM`, `SETGOE`
  * `SETGOPN`, `SETGOMN`, `SETGOEN`
  * `SETGOPT`, `SETGOMT`, `SETGOET`
  * `SETGOPTN`, `SETGOMTN`, `SETGOETN`

as blogged about here:
*
https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/future-architecture-technologies-poe2-and-vmte

and as documented here:
*
https://developer.arm.com/documentation/109697/2025_09/Future-Architecture-Technologies

Identified with readability-container-contains.

STAR-MC3 is an Armv8.1m CPU.
Technical specificationa available at:
https://www.armchina.com/download/Documents/TRM?infoId=240

Add support for new Advanced SIMD (Neon) instructions:

 - FDOT (half-precision to single-precision, by element)
 - FDOT (half-precision to single-precision, vector)
 - FMMLA (half-precision, non-widening)
 - FMMLA (widening, half-precision to single-precision)

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

Co-authored-by: Kerry McLaughlin <kerry.mclaughlin@arm.com>
Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>

Add instructions for SVE2p3 DOT and MLA operations:

  - BFMMLA (non-widening)
  - FMMLA (non-widening)
  - SDOT (2-way, vectors)
  - SDOT (2-way, indexed)
  - UDOT (2-way, vectors)
  - UDOT (2-way, indexed)

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

Add instructions for SVE2p3 arithmetic operations:

  - `ADDQP`    (add pairwise within quadword vector segments)
  - `ADDSUBP`  (add subtract pairwise)
  - `SABAL`    (two-way signed absolute difference sum and accumulate long)
  - `SUBP`     (subtract pairwise)
  - `UABAL`    (two-way unsigned absolute difference sum and accumulate long)

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions

Add new instruction and system registers that are specified in the
Generic Interrupt Controller Architecture v5 (GICv5) standard,
announced here:

   * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/introducing-gicv5

and documented here:

   * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
   * https://developer.arm.com/documentation/ddi0602/2025-09/

Co-authored-by: Jack Styles <jack.styles@arm.com>

Add the following instructions for `FEAT_MTETC`, which is a part of
`FEAT_VMTE` for Virtual Tagging:
  * `DC ZGBVA`
  * `DC GBVA`

as documented here:

  * https://developer.arm.com/documentation/ddi0602/2025-09/
  * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions