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<title>llvm-project.git/llvm/unittests/CodeGen/MachineInstrTest.cpp, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119487)</title>
<updated>2024-12-11T21:17:32+00:00</updated>
<author>
<name>Owen Anderson</name>
<email>resistor@mac.com</email>
</author>
<published>2024-12-11T21:17:32+00:00</published>
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<id>6f3f08abdc9faac1fe07018bf72d532443f2ec05</id>
<content type='text'>
This reapplies #119122 with a fix for UBSAN errors in the X86 backend
related
to incrementing a nullptr.</content>
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This reapplies #119122 with a fix for UBSAN errors in the X86 backend
related
to incrementing a nullptr.</pre>
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</entry>
<entry>
<title>Revert "CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)"</title>
<updated>2024-12-11T00:45:17+00:00</updated>
<author>
<name>Owen Anderson</name>
<email>resistor@mac.com</email>
</author>
<published>2024-12-11T00:44:07+00:00</published>
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<id>e940353fd2ac9817d3506744b309d857e76c0afa</id>
<content type='text'>
Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass

This reverts commit c4873819a98f59ce4e2664f94c73c2dfec3393f8.
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<pre>
Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass

This reverts commit c4873819a98f59ce4e2664f94c73c2dfec3393f8.
</pre>
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</entry>
<entry>
<title>CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)</title>
<updated>2024-12-10T23:36:51+00:00</updated>
<author>
<name>Owen Anderson</name>
<email>resistor@mac.com</email>
</author>
<published>2024-12-10T23:36:51+00:00</published>
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<id>c4873819a98f59ce4e2664f94c73c2dfec3393f8</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234)</title>
<updated>2024-11-14T21:30:05+00:00</updated>
<author>
<name>Matin Raayai</name>
<email>30674652+matinraayai@users.noreply.github.com</email>
</author>
<published>2024-11-14T21:30:05+00:00</published>
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<id>bb3f5e1fed7c6ba733b7f273e93f5d3930976185</id>
<content type='text'>
Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks</content>
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<pre>
Following discussions in #110443, and the following earlier discussions
in https://lists.llvm.org/pipermail/llvm-dev/2017-October/117907.html,
https://reviews.llvm.org/D38482, https://reviews.llvm.org/D38489, this
PR attempts to overhaul the `TargetMachine` and `LLVMTargetMachine`
interface classes. More specifically:
1. Makes `TargetMachine` the only class implemented under
`TargetMachine.h` in the `Target` library.
2. `TargetMachine` contains target-specific interface functions that
relate to IR/CodeGen/MC constructs, whereas before (at least on paper)
it was supposed to have only IR/MC constructs. Any Target that doesn't
want to use the independent code generator simply does not implement
them, and returns either `false` or `nullptr`.
3. Renames `LLVMTargetMachine` to `CodeGenCommonTMImpl`. This renaming
aims to make the purpose of `LLVMTargetMachine` clearer. Its interface
was moved under the CodeGen library, to further emphasis its usage in
Targets that use CodeGen directly.
4. Makes `TargetMachine` the only interface used across LLVM and its
projects. With these changes, `CodeGenCommonTMImpl` is simply a set of
shared function implementations of `TargetMachine`, and CodeGen users
don't need to static cast to `LLVMTargetMachine` every time they need a
CodeGen-specific feature of the `TargetMachine`.
5. More importantly, does not change any requirements regarding library
linking.

cc @arsenm @aeubanks</pre>
</div>
</content>
</entry>
<entry>
<title>[unittests] Use {} instead of std::nullopt to initialize empty ArrayRef (#109388)</title>
<updated>2024-09-21T09:59:50+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-09-21T09:59:50+00:00</published>
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<id>eb6e7e8f89a3d5c1cbc9856774ca00208753fb12</id>
<content type='text'>
Follow up to #109133.</content>
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Follow up to #109133.</pre>
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</entry>
<entry>
<title>[llvm][unittests] Strip unneeded uses of raw_string_ostream::str() (NFC)</title>
<updated>2024-09-13T13:42:32+00:00</updated>
<author>
<name>JOE1994</name>
<email>joseph942010@gmail.com</email>
</author>
<published>2024-09-13T13:35:57+00:00</published>
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<id>387bee91f095c197270b4d0a9e19cc86b2edea73</id>
<content type='text'>
Avoid excess layer of indirection.
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<pre>
Avoid excess layer of indirection.
</pre>
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</content>
</entry>
<entry>
<title>[IRBuilder] Don't include Module.h (NFC) (#97159)</title>
<updated>2024-06-29T13:05:04+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>llvm@npopov.com</email>
</author>
<published>2024-06-29T13:05:04+00:00</published>
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<id>74deadf19650f6f3b6392ba09caa20dd38ae41e0</id>
<content type='text'>
This used to be necessary to fetch the DataLayout, but isn't anymore.</content>
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This used to be necessary to fetch the DataLayout, but isn't anymore.</pre>
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</content>
</entry>
<entry>
<title>[IR] Memory Model Relaxation Annotations (#78569)</title>
<updated>2024-04-24T06:52:25+00:00</updated>
<author>
<name>Pierre van Houtryve</name>
<email>pierre.vanhoutryve@amd.com</email>
</author>
<published>2024-04-24T06:52:25+00:00</published>
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<id>cf328ff96daf5e676fb51ac86e550af7fd689fec</id>
<content type='text'>
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.

RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5</content>
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<pre>
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.

RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Speed up SIRegisterInfo::getReservedRegs (#79844)</title>
<updated>2024-01-30T11:32:16+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2024-01-30T11:32:16+00:00</published>
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<id>0e17684cf5ce3b99e8f732f53c3534990ad91fd5</id>
<content type='text'>
reserveRegisterTuples is slow because it uses MCRegAliasIterator and
hence ends up reserving the same aliased registers many times. This
patch changes getReservedRegs not to use it for reserving SGPRs, VGPRs
and AGPRs. Instead it iterates through base register classes, which
should come closer to reserving each register once only.

Overall this speeds up the time to run check-llvm-codegen-amdgpu in my
Release build from 18.4 seconds to 16.9 seconds (all timings +/- 0.2).</content>
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<pre>
reserveRegisterTuples is slow because it uses MCRegAliasIterator and
hence ends up reserving the same aliased registers many times. This
patch changes getReservedRegs not to use it for reserving SGPRs, VGPRs
and AGPRs. Instead it iterates through base register classes, which
should come closer to reserving each register once only.

Overall this speeds up the time to run check-llvm-codegen-amdgpu in my
Release build from 18.4 seconds to 16.9 seconds (all timings +/- 0.2).</pre>
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</content>
</entry>
<entry>
<title>[llvm] Use StringRef::{starts,ends}_with (NFC)</title>
<updated>2023-12-14T06:46:02+00:00</updated>
<author>
<name>Kazu Hirata</name>
<email>kazu@google.com</email>
</author>
<published>2023-12-14T06:46:02+00:00</published>
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<id>5c9d82de6b72cc0c037daecce452c450870f0034</id>
<content type='text'>
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
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<pre>
This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.
</pre>
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</entry>
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