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<title>llvm-project.git/llvm/test/Transforms/LoopVectorize/reduction-predselect.ll, branch users/nico/python-2</title>
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<entry>
<title>[InstCombine] Handle "add like" in ADD+GEP-&gt;GEP+GEP rewrites (#135156)</title>
<updated>2025-04-14T15:11:13+00:00</updated>
<author>
<name>Björn Pettersson</name>
<email>bjorn.a.pettersson@ericsson.com</email>
</author>
<published>2025-04-14T15:11:13+00:00</published>
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<id>092b6e73e651469527662443b592f98f442ece72</id>
<content type='text'>
Considering that "or disjoint" is the canonical for certain add
operations, then I think we want to support such "add like" operations
when doing ADD+GEP-&gt;GEP+GEP rewrites to make things more consistent.

Problem was found when improving ValueTracking, which turned an ADD into
OR, and then suddenly optimizations got worse due to these rewrites no
longer triggering.</content>
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<pre>
Considering that "or disjoint" is the canonical for certain add
operations, then I think we want to support such "add like" operations
when doing ADD+GEP-&gt;GEP+GEP rewrites to make things more consistent.

Problem was found when improving ValueTracking, which turned an ADD into
OR, and then suddenly optimizations got worse due to these rewrites no
longer triggering.</pre>
</div>
</content>
</entry>
<entry>
<title>[VPlan] Add initial CFG simplification, removing BranchOnCond true. (#106748)</title>
<updated>2025-04-04T14:44:26+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2025-04-04T14:44:26+00:00</published>
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<id>5fbd0658a02bd91cf36419f2f425732a06315432</id>
<content type='text'>
Add an initial CFG simplification transform, which removes the dead
edges for blocks terminated with BranchOnCond true.

At the moment, this removes the edge between middle block and scalar
preheader when folding the tail.

PR: https://github.com/llvm/llvm-project/pull/106748</content>
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<pre>
Add an initial CFG simplification transform, which removes the dead
edges for blocks terminated with BranchOnCond true.

At the moment, this removes the edge between middle block and scalar
preheader when folding the tail.

PR: https://github.com/llvm/llvm-project/pull/106748</pre>
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</content>
</entry>
<entry>
<title>[LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (#118828)</title>
<updated>2025-03-28T14:47:40+00:00</updated>
<author>
<name>Hari Limaye</name>
<email>hari.limaye@arm.com</email>
</author>
<published>2025-03-28T14:47:40+00:00</published>
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<id>bf5627c85e6975a73bf582cf0d23a993673413d0</id>
<content type='text'>
Optimize the IR generated for a VPWidenIntOrFpInductionRecipe to use the
narrowest type necessary, when the trip-count of a loop is known to be
constant and the only use of the recipe is the condition used by the
vector loop's backedge branch.</content>
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<pre>
Optimize the IR generated for a VPWidenIntOrFpInductionRecipe to use the
narrowest type necessary, when the trip-count of a loop is known to be
constant and the only use of the recipe is the condition used by the
vector loop's backedge branch.</pre>
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</content>
</entry>
<entry>
<title>[LV] Use IVUpdateMayOverflow to set HasNUW. (#111758)</title>
<updated>2024-11-28T10:12:41+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2024-11-28T10:12:41+00:00</published>
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<id>82821254f532c1dbdfd5d985ef7130511efaaa83</id>
<content type='text'>
If IVUpdateMayOverflow is false, we proved that the induction increment
cannot overflow in the vector loop. This allows setting NUW in some
cases when folding the tail.

PR: https://github.com/llvm/llvm-project/pull/111758</content>
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<pre>
If IVUpdateMayOverflow is false, we proved that the induction increment
cannot overflow in the vector loop. This allows setting NUW in some
cases when folding the tail.

PR: https://github.com/llvm/llvm-project/pull/111758</pre>
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</content>
</entry>
<entry>
<title>[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)</title>
<updated>2024-11-06T11:53:33+00:00</updated>
<author>
<name>Paul Walker</name>
<email>paul.walker@arm.com</email>
</author>
<published>2024-11-06T11:53:33+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>Prefer use of 0.0 over -0.0 for fadd reductions w/nsz (in IR) (#106770)</title>
<updated>2024-09-03T16:16:37+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2024-09-03T16:16:37+00:00</published>
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<id>2c7786e94a1058bd4f96794a1d4f70dcb86e5cc5</id>
<content type='text'>
This is a follow up to 924907bc6, and is mostly motivated by consistency
but does include one additional optimization. In general, we prefer 0.0
over -0.0 as the identity value for an fadd. We use that value in
several places, but don't in others. So, let's be consistent and use the
same identity (when nsz allows) everywhere.

This creates a bunch of test churn, but due to 924907bc6, most of that
churn doesn't actually indicate a change in codegen. The exception is
that this change enables the use of 0.0 for nsz, but *not* reasoc, fadd
reductions. Or said differently, it allows the neutral value of an
ordered fadd reduction to be 0.0.</content>
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<pre>
This is a follow up to 924907bc6, and is mostly motivated by consistency
but does include one additional optimization. In general, we prefer 0.0
over -0.0 as the identity value for an fadd. We use that value in
several places, but don't in others. So, let's be consistent and use the
same identity (when nsz allows) everywhere.

This creates a bunch of test churn, but due to 924907bc6, most of that
churn doesn't actually indicate a change in codegen. The exception is
that this change enables the use of 0.0 for nsz, but *not* reasoc, fadd
reductions. Or said differently, it allows the neutral value of an
ordered fadd reduction to be 0.0.</pre>
</div>
</content>
</entry>
<entry>
<title>Regen a bunch of vectorizer tests to avoid naming churn in upcoming review</title>
<updated>2024-08-30T17:13:02+00:00</updated>
<author>
<name>Philip Reames</name>
<email>preames@rivosinc.com</email>
</author>
<published>2024-08-30T17:08:51+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[InstCombine] Set disjoint flag when turning Add into Or. (#72702)</title>
<updated>2023-11-27T20:54:11+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2023-11-27T20:54:11+00:00</published>
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<id>03d4a9d94da30590ebfc444cf13a8763f47b7bb9</id>
<content type='text'>
The disjoint flag was recently added to IR in #72583 </content>
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<pre>
The disjoint flag was recently added to IR in #72583 </pre>
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</content>
</entry>
<entry>
<title>[LoopVectorize] Convert some tests to opaque pointers (NFC)</title>
<updated>2022-12-14T14:16:59+00:00</updated>
<author>
<name>Nikita Popov</name>
<email>npopov@redhat.com</email>
</author>
<published>2022-12-14T14:15:18+00:00</published>
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<id>7d7577256b76e4293f455b8093504d5f7044ab4b</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[NFC] Port all runlines for LoopVectorize pass tests to -passes syntax</title>
<updated>2022-12-05T19:17:30+00:00</updated>
<author>
<name>Roman Lebedev</name>
<email>lebedev.ri@gmail.com</email>
</author>
<published>2022-12-05T18:44:25+00:00</published>
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<pre>
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