llvm-project.git/llvm/test/Transforms/LoopVectorize/minmax_reduction.ll, branch users/nico/python-2

[LV] Add support for minimum/maximum intrinsics

2023-06-20T17:17:28+00:00

{mini|maxi}mum intrinsics are different from {min|max}num intrinsics in
the propagation of NaN and signed zero. Also, the minnum/maxnum
intrinsics require the presence of nsz flags to be valid reductions in
vectorizer. In this regard, we introduce a new recurrence kind and also
add support for identifying reduction patterns using these intrinsics.

The reduction intrinsics and lowering was introduced here: 26bfbec5d2.

There are tests added which show how this interacts across chains of
min/max patterns.

Differential Revision: https://reviews.llvm.org/D151482

[IRBuilder] Use canonical i64 type for insertelement index used by vector splats.

2023-01-11T14:08:06+00:00

Instcombine prefers this canonical form (see getPreferredVectorIndex),
as does IRBuilder when passing the index as an integer so we may as
well use the prefered form from creation.

NOTE: All test changes are mechanical with nothing else expected
beyond a change of index type from i32 to i64.

Differential Revision: https://reviews.llvm.org/D140983

[LoopVectorize] Convert some tests to opaque pointers (NFC)

2022-12-14T14:16:59+00:00

[NFC] Port all runlines for LoopVectorize pass tests to -passes syntax

2022-12-05T19:17:30+00:00

[LV] Recognize intrinsic min/max reductions

2021-09-15T09:45:50+00:00

This extends the reduction logic in the vectorizer to handle intrinsic
versions of min and max, both the floating point variants already
created by instcombine under fastmath and the integer variants from
D98152.

As a bonus this allows us to match a chain of min or max operations into
a single reduction, similar to how add/mul/etc work.

Differential Revision: https://reviews.llvm.org/D109645

[LV] Min/max intrinsic reduction test cases.

2021-09-15T08:56:19+00:00

[LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax

2021-02-15T13:47:05+00:00

Currently, setting the `no-nans-fp-math` attribute to true will allow
loops with fmin/fmax to vectorize, though we should be requiring that
`no-signed-zeros-fp-math` is also set.

This patch adds the check for no-signed-zeros at the function level and includes
tests to make sure we don't vectorize functions with only one of the attributes
associated.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D96604

[Vectorizers][TTI] remove option to bypass creation of vector reduction intrinsics

2021-02-12T13:13:50+00:00

The vector reduction intrinsics started life as experimental ops, so backend support
was lacking. As part of promoting them to 1st-class intrinsics, however, codegen
support was added/improved:
D58015
D90247

So I think it is safe to now remove this complication from IR.

Note that we still have an IR-level codegen expansion pass for these as discussed
in D95690. Removing that is another step in simplifying the logic. Also note that
x86 was already unconditionally forming reductions in IR, so there should be no
difference for x86.

I spot checked a couple of the tests here by running them through opt+llc and did
not see any asm diffs.

If we do find functional differences for other targets, it should be possible
to (at least temporarily) restore the shuffle IR with the ExpandReductions IR
pass.

Differential Revision: https://reviews.llvm.org/D96552

[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder

2020-12-29T19:21:04+00:00

This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D93793

[LoopVectorize] update test to be independent of instcombine; NFC

2019-05-24T16:46:09+00:00

This is a regression test for vectorization, so remove instcombine
from the RUN line and adjust the comparison predicates to show what
the vectorizer is creating rather than how instcombine cleans it up.

llvm-svn: 361648