llvm-project.git/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll, branch users/nico/python-2

[InstCombine] Handle "add like" in ADD+GEP->GEP+GEP rewrites (#135156)

2025-04-14T15:11:13+00:00

Considering that "or disjoint" is the canonical for certain add
operations, then I think we want to support such "add like" operations
when doing ADD+GEP->GEP+GEP rewrites to make things more consistent.

Problem was found when improving ValueTracking, which turned an ADD into
OR, and then suddenly optimizations got worse due to these rewrites no
longer triggering.

[VPlan] Add incoming values for all predecessor to ResumePHI (NFCI).

2025-02-09T11:20:20+00:00

Follow-up as discussed when using VPInstruction::ResumePhi for all resume
values (#112147). This patch explicitly adds incoming values for each
predecessor in VPlan. This simplifies codegen and allows transformations
adjusting the predecessors of blocks with

NFC modulo incoming block order in phis.

[VPlan] Compute induction end values in VPlan. (#112145)

2024-12-29T19:05:08+00:00

Use createDerivedIV to compute IV end values directly in VPlan, instead
of creating them up-front.

This allows updating IV users outside the loop as follow-up.

Depends on https://github.com/llvm/llvm-project/pull/110004 and
https://github.com/llvm/llvm-project/pull/109975.

PR: https://github.com/llvm/llvm-project/pull/112145

Revert "[InstCombine] Infer nuw for gep inbounds from base of object" (#120460)

2024-12-18T18:06:34+00:00

Reverts llvm/llvm-project#119225 due to the lack of sanitizer support,
large potential of breaking code containing latent UB, non-trivial
localization and investigation, and what seems to be a bad interaction
with msan (a test is in the works).

Related discussions:
https://github.com/llvm/llvm-project/pull/119225#issuecomment-2551904822
https://github.com/llvm/llvm-project/pull/118472#issuecomment-2549986255

[VPlan] Remove reverse() of predecessors from VPInstruction::generate.

2024-12-17T20:44:32+00:00

This was originally done to reduce the diff for the change. Remove it
and update the remaining tests. NFC modulo reordering of incoming
values.

Clean up after https://github.com/llvm/llvm-project/pull/114292.

[InstCombine] Infer nuw for gep inbounds from base of object (#119225)

2024-12-10T09:00:50+00:00

When we have a gep inbounds from the base of an object (e.g. alloca or
global), we know that the index cannot be negative, as this would go out
of bounds. As such, we can infer nuw as well.

The implementation is a bit stricter than necessary, we could also
accept one unknown index followed by known-non-negative indices.

Proof: https://alive2.llvm.org/ce/z/Hp7-6w (Note that alive2 currently
incorrectly doesn't require the inbounds for the alloca case, see
https://github.com/AliveToolkit/alive2/issues/1138).

[InstCombine] Infer nusw + nneg -> nuw for getelementptr (#111144)

2024-12-05T13:36:40+00:00

If the gep is nusw (usually via inbounds) and the offset is
non-negative, we can infer nuw.

Proof: https://alive2.llvm.org/ce/z/ihztLy

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06T11:53:33+00:00

[InstCombine] Set `samesign` when converting signed predicates into unsigned (#112642)

2024-10-17T12:43:48+00:00

Alive2: https://alive2.llvm.org/ce/z/6cqdt-

[VPlan] Use pointer to member 0 as VPInterleaveRecipe's pointer arg. (#106431)

2024-10-06T21:53:13+00:00

Update VPInterleaveRecipe to always use the pointer to member 0 as
pointer argument. This in many cases helps to remove unneeded index
adjustments and simplifies VPInterleaveRecipe::execute.

In some rare cases, the address of member 0 does not dominate the insert
position of the interleave group. In those cases a PtrAdd VPInstruction
is emitted to compute the address of member 0 based on the address of
the insert position. Alternatively we could hoist the recipe computing
the address of member 0.