llvm-project.git/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll, branch users/nico/python-2

[VPlan] Generalize SCALAR-STEPS removal to any unroll factor.

2025-03-26T21:03:50+00:00

Follow-up to dfca6c0d3bf9d1a056 to extend isUnrolled handle any unrolled
VPlan, which means there's a single UF, but it will be > 1 if unrolling
took place.

[VPlan] Remove no-op SCALAR-STEPS after unrolling. (#123655)

2025-03-25T12:57:24+00:00

After unrolling, there may be additional simplifications that can be
applied. One example is removing SCALAR-STEPS for the first part where
only the first lane is demanded.

This removes redundant adds of 0 from a large number of tests (~200),
many which I am still working on updating.

In preparation for removing redundant WideIV steps added in
https://github.com/llvm/llvm-project/pull/119284.

PR: https://github.com/llvm/llvm-project/pull/123655

[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)

2024-11-06T11:53:33+00:00

[VPlan] Run DCE after unrolling.

2024-09-22T21:08:46+00:00

This cleans up a number of dead recipes after unrolling if only their
first or last parts are used. This simplifies a number of tests.

Fixes https://github.com/llvm/llvm-project/issues/109581.

[LV] Only OR unique edges when creating block-in masks.

2024-08-12T09:17:40+00:00

This removes redundant ORs of matching masks.

Follow-up to f0df4fbd0c7b to reduce the number of redundant ORs for
masks.

[VPlan] Mark VPVectorPointer as only using the first part of the ptr.

2024-08-12T07:46:55+00:00

VPVectorPointerRecipe only uses the first part of the pointer operand,
so mark it accordingly.

Follow-up suggested as part of
https://github.com/llvm/llvm-project/pull/99808.

[LV] Handle SwitchInst in ::isPredicatedInst.

2024-08-11T19:56:58+00:00

After f0df4fbd0c7b, isPredicatedInst needs to handle SwitchInst as well.
Handle it the same as BranchInst.

This fixes a crash in the newly added test and improves the results for
one of the existing tests in predicate-switch.ll

Should fix https://lab.llvm.org/buildbot/#/builders/113/builds/2099.

[LV] Support generating masks for switch terminators. (#99808)

2024-08-11T18:38:36+00:00

Update createEdgeMask to created masks where the terminator in Src is a
switch. We need to handle 2 separate cases:

1. Dst is not the default desintation. Dst is reached if any of the
cases with destination == Dst are taken. Join the conditions for each
case where destination == Dst using a logical OR.
2. Dst is the default destination. Dst is reached if none of the cases
with destination != Dst are taken. Join the conditions for each case
where the destination is != Dst using a logical OR and negate it.

Edge masks are created for every destination of cases and/or 
default when requesting a mask where the source is a switch.

Fixes https://github.com/llvm/llvm-project/issues/48188.

PR: https://github.com/llvm/llvm-project/pull/99808

[LV] Add more tests with switches.

2024-08-01T18:30:48+00:00

Extra tests for
https://github.com/llvm/llvm-project/pull/99808, including cost model
tests.

[LV] Add tests for loops with switches.

2024-07-21T09:11:38+00:00