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<title>llvm-project.git/llvm/test/Transforms/InferAddressSpaces, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>Reapply "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (#137488)""</title>
<updated>2025-05-31T02:11:22+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-31T02:11:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4d48673562163d99dec601a40dc79aa30102d088'/>
<id>4d48673562163d99dec601a40dc79aa30102d088</id>
<content type='text'>
This reverts commit 37ea3b32cdcb6c0dcecbcc4bf844f5190c7378dd.
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<pre>
This reverts commit 37ea3b32cdcb6c0dcecbcc4bf844f5190c7378dd.
</pre>
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</entry>
<entry>
<title>Revert "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (#137488)""</title>
<updated>2025-05-31T02:06:16+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-31T02:06:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=37ea3b32cdcb6c0dcecbcc4bf844f5190c7378dd'/>
<id>37ea3b32cdcb6c0dcecbcc4bf844f5190c7378dd</id>
<content type='text'>
This reverts commit 4efc13f8ff1eaf4f9fb1fcea8d4552b3eca052ca.
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<pre>
This reverts commit 4efc13f8ff1eaf4f9fb1fcea8d4552b3eca052ca.
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</entry>
<entry>
<title>Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (#137488)"</title>
<updated>2025-05-31T01:56:24+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-31T01:56:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4efc13f8ff1eaf4f9fb1fcea8d4552b3eca052ca'/>
<id>4efc13f8ff1eaf4f9fb1fcea8d4552b3eca052ca</id>
<content type='text'>
This reverts commit 3c6211c183885afb5d89259a53c4f4f46a6bf399.
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<pre>
This reverts commit 3c6211c183885afb5d89259a53c4f4f46a6bf399.
</pre>
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</entry>
<entry>
<title>Revert "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (#137488)"</title>
<updated>2025-05-31T01:15:25+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-31T01:15:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3c6211c183885afb5d89259a53c4f4f46a6bf399'/>
<id>3c6211c183885afb5d89259a53c4f4f46a6bf399</id>
<content type='text'>
This reverts commit 9bf6b2a8cb0467b62173659306e43a0346f063a2.
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<pre>
This reverts commit 9bf6b2a8cb0467b62173659306e43a0346f063a2.
</pre>
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</entry>
<entry>
<title>[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (#137488)</title>
<updated>2025-05-30T21:30:42+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-30T21:30:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=9bf6b2a8cb0467b62173659306e43a0346f063a2'/>
<id>9bf6b2a8cb0467b62173659306e43a0346f063a2</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604)</title>
<updated>2025-05-29T21:20:56+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-29T21:20:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=84a69a0f8f60b6d852b9a16be199bfa432706b0c'/>
<id>84a69a0f8f60b6d852b9a16be199bfa432706b0c</id>
<content type='text'>
It will run twice in the non-LTO pipeline with `O1` or higher. In LTO post link pipeline, it will be run once with `O2` or higher, since inline and SROA don't run in `O1`.
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<pre>
It will run twice in the non-LTO pipeline with `O1` or higher. In LTO post link pipeline, it will be run once with `O2` or higher, since inline and SROA don't run in `O1`.
</pre>
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</content>
</entry>
<entry>
<title>[NFC][AMDGPU] Move `flat_atomic.ll` to `llvm/test/CodeGen/AMDGPU/` (#141126)</title>
<updated>2025-05-23T12:15:26+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-05-23T12:15:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0f1277d0b3e391b7d8bbe20b7c0b04d3708415ec'/>
<id>0f1277d0b3e391b7d8bbe20b7c0b04d3708415ec</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[InferAddressSpaces] Handle llvm.lifetime (#141045)</title>
<updated>2025-05-22T16:06:01+00:00</updated>
<author>
<name>QiYue</name>
<email>yangzhh@mail.ustc.edu.cn</email>
</author>
<published>2025-05-22T16:06:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=758fea0e995e6128022e5cd2605a92222e130837'/>
<id>758fea0e995e6128022e5cd2605a92222e130837</id>
<content type='text'>
Co-authored-by: Zhenhao Yang &lt;zhenhao.yang@nio.com&gt;
Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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<pre>
Co-authored-by: Zhenhao Yang &lt;zhenhao.yang@nio.com&gt;
Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Add make.buffer.rsrc to InferAddressSpaces (#140770)</title>
<updated>2025-05-20T23:13:37+00:00</updated>
<author>
<name>Krzysztof Drewniak</name>
<email>Krzysztof.Drewniak@amd.com</email>
</author>
<published>2025-05-20T23:13:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=13c467b2cdc0e185671875a0d8e53a420382c73d'/>
<id>13c467b2cdc0e185671875a0d8e53a420382c73d</id>
<content type='text'>
make.buffer.rsrc can be subjected to address space inference. There's
not _currently_ a reason to have this, but we might as well handle this
in case it comes up.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</content>
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<pre>
make.buffer.rsrc can be subjected to address space inference. There's
not _currently_ a reason to have this, but we might as well handle this
in case it comes up.

---------

Co-authored-by: Matt Arsenault &lt;arsenm2@gmail.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Set AS8 address width to 48 bits</title>
<updated>2025-05-20T00:26:05+00:00</updated>
<author>
<name>Alexander Richardson</name>
<email>alexrichardson@google.com</email>
</author>
<published>2025-05-20T00:26:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=07e2ba445df7d277e5195c0ec85b133735ea76e3'/>
<id>07e2ba445df7d277e5195c0ec85b133735ea76e3</id>
<content type='text'>
Of the 128-bits of buffer descriptor only 48 bits are address bits, so
following the discussion on https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54,
the logic conclusion is to set the index width to 48 bits instead of
the current value of 128.

Most of the test changes are mechanical datalayout updates, but there
is one actual change: the ptrmask test now uses .i48 instead of .i128
and I had to update SelectionDAGBuilder to correctly extend the mask.

Reviewed By: krzysz00

Pull Request: https://github.com/llvm/llvm-project/pull/139419
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Of the 128-bits of buffer descriptor only 48 bits are address bits, so
following the discussion on https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54,
the logic conclusion is to set the index width to 48 bits instead of
the current value of 128.

Most of the test changes are mechanical datalayout updates, but there
is one actual change: the ptrmask test now uses .i48 instead of .i128
and I had to update SelectionDAGBuilder to correctly extend the mask.

Reviewed By: krzysz00

Pull Request: https://github.com/llvm/llvm-project/pull/139419
</pre>
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</content>
</entry>
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