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<title>llvm-project.git/llvm/test/Transforms/IndVarSimplify, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[SCEV] Better preserve wrapping info in SimplifyICmpOperands for UGE. (#144404)</title>
<updated>2025-06-17T14:30:08+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2025-06-17T14:30:08+00:00</published>
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<id>8f797542258f6e682eb251d0851922a1ac08fb44</id>
<content type='text'>
Update SimplifyICmpOperands to only try subtracting 1 from RHS first, if
RHS is an op we can fold the subtract directly into. Otherwise try
adding to LHS first, as we can preserve NUW flags.

This improves results in a few cases, including the modified test case
from berkeley-abc and new code to be added in
https://github.com/llvm/llvm-project/pull/128061.

Note that there are more cases where the results can be improved by
better ordering here which I'll try to investigate as follow-up.

PR: https://github.com/llvm/llvm-project/pull/144404</content>
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<pre>
Update SimplifyICmpOperands to only try subtracting 1 from RHS first, if
RHS is an op we can fold the subtract directly into. Otherwise try
adding to LHS first, as we can preserve NUW flags.

This improves results in a few cases, including the modified test case
from berkeley-abc and new code to be added in
https://github.com/llvm/llvm-project/pull/128061.

Note that there are more cases where the results can be improved by
better ordering here which I'll try to investigate as follow-up.

PR: https://github.com/llvm/llvm-project/pull/144404</pre>
</div>
</content>
</entry>
<entry>
<title>[IndVars] Add tests showing missed simplifications.</title>
<updated>2025-06-16T15:31:21+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2025-06-16T15:31:20+00:00</published>
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</pre>
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</entry>
<entry>
<title>[IndVars] Teach widenLoopCompare to use sext if narrow IV is positive and other operand is already sext. (#142703)</title>
<updated>2025-06-10T19:52:39+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-06-10T19:52:39+00:00</published>
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<id>e0cc556ad4276c2c76e303c39616ad126bea56d6</id>
<content type='text'>
This prevents us from ending up with (zext (sext X)). The zext will
require an instruction on targets where zext isn't free like RISC-V.</content>
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<pre>
This prevents us from ending up with (zext (sext X)). The zext will
require an instruction on targets where zext isn't free like RISC-V.</pre>
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</content>
</entry>
<entry>
<title>[SCEV] Add more tests with zext(add C, %var)&lt;nsw&gt;.</title>
<updated>2025-06-03T21:03:20+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2025-06-03T21:03:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=1340ecf0ba4b38bae9de9781da72b9a72abd3fbe'/>
<id>1340ecf0ba4b38bae9de9781da72b9a72abd3fbe</id>
<content type='text'>
Add extra test coverage for
https://github.com/llvm/llvm-project/pull/142599.
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Add extra test coverage for
https://github.com/llvm/llvm-project/pull/142599.
</pre>
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</content>
</entry>
<entry>
<title>[SCEV] Add additional test coverage for loop-guards reasoning.</title>
<updated>2025-06-01T21:39:37+00:00</updated>
<author>
<name>Florian Hahn</name>
<email>flo@fhahn.com</email>
</author>
<published>2025-06-01T21:38:33+00:00</published>
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<id>0ba63b2f22bfb00848ec2d71fbc11cf52b93a290</id>
<content type='text'>
Add additional tests showing missed opportunities when using loop guards
for reasoning in SCEV, depending on the order the guards appear in the
IR.
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<pre>
Add additional tests showing missed opportunities when using loop guards
for reasoning in SCEV, depending on the order the guards appear in the
IR.
</pre>
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</content>
</entry>
<entry>
<title>[IndVarSimplify] Set samesign when converting signed comparison to unsigned comparison in eliminateIVComparison. (#138215)</title>
<updated>2025-05-02T15:17:45+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-05-02T15:17:45+00:00</published>
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</entry>
<entry>
<title>[AMDGPU] Remove explicit datalayout from tests where not needed</title>
<updated>2025-04-30T17:58:17+00:00</updated>
<author>
<name>Alexander Richardson</name>
<email>alexrichardson@google.com</email>
</author>
<published>2025-04-30T17:58:17+00:00</published>
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<id>ee136383628290f7efa0fc4562beef2b411048bb</id>
<content type='text'>
Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.

Reviewed By: shiltian, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/137921
</content>
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<pre>
Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.

Reviewed By: shiltian, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/137921
</pre>
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</content>
</entry>
<entry>
<title>[IndVarsSimplify] sinkUnusedInvariants is skipping instructions while sinking. (#135205)</title>
<updated>2025-04-18T00:21:18+00:00</updated>
<author>
<name>Sirish Pande</name>
<email>sirpande@amd.com</email>
</author>
<published>2025-04-18T00:21:18+00:00</published>
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<id>7f107c301963ad1070f2130f89655fd94f2c0714</id>
<content type='text'>
While sinking instructions (that are loop invariant) from preheader to
the exit block, we are skipping instructions due to decrementing
instruction iterator twice.</content>
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<pre>
While sinking instructions (that are loop invariant) from preheader to
the exit block, we are skipping instructions due to decrementing
instruction iterator twice.</pre>
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</content>
</entry>
<entry>
<title>[DebugInfo][IndVarSimplify] Propagate source loc when simplifying rem (#135399)</title>
<updated>2025-04-17T16:30:09+00:00</updated>
<author>
<name>Stephen Tozer</name>
<email>stephen.tozer@sony.com</email>
</author>
<published>2025-04-17T16:30:09+00:00</published>
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<id>1f224d889dfa89a293e3efa5b04740f634454370</id>
<content type='text'>
When IndVarSimplify simplifies a rem of the induction variable to a cmp
and select, only the select currently receives the rem's source
location; this patch propagates it to the cmp as well.

Found using https://github.com/llvm/llvm-project/pull/107279.</content>
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<pre>
When IndVarSimplify simplifies a rem of the induction variable to a cmp
and select, only the select currently receives the rem's source
location; this patch propagates it to the cmp as well.

Found using https://github.com/llvm/llvm-project/pull/107279.</pre>
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</content>
</entry>
<entry>
<title>[IndVarSimplify] Handle the case where both operands are the same when widening IV (#135207)</title>
<updated>2025-04-11T01:03:06+00:00</updated>
<author>
<name>Yingwei Zheng</name>
<email>dtcxzyw2333@gmail.com</email>
</author>
<published>2025-04-11T01:03:06+00:00</published>
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<id>d14acb78065bdd331019924feaaef52e5e744529</id>
<content type='text'>
`WidenIV::widenWithVariantUse` assumes that exactly one of the binop
operands is the IV to be widened. This miscompilation happens when it
tries to sign-extend the "NonIV" operand while the IV is zero-extended.
Closes https://github.com/llvm/llvm-project/issues/135182.
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<pre>
`WidenIV::widenWithVariantUse` assumes that exactly one of the binop
operands is the IV to be widened. This miscompilation happens when it
tries to sign-extend the "NonIV" operand while the IV is zero-extended.
Closes https://github.com/llvm/llvm-project/issues/135182.
</pre>
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</content>
</entry>
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