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<title>llvm-project.git/llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir, branch users/mingmingl-llvm/samplefdo-profile-format</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[AMDGPU] Remove most uses of /dev/null in tests (#156630)</title>
<updated>2025-09-03T15:39:29+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-09-03T15:39:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fee17b3a96c29ddef59103bd7c02568f748e37ab'/>
<id>fee17b3a96c29ddef59103bd7c02568f748e37ab</id>
<content type='text'>
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU,test] Change llc -march= to -mtriple=</title>
<updated>2024-03-08T03:09:18+00:00</updated>
<author>
<name>Fangrui Song</name>
<email>i@maskray.me</email>
</author>
<published>2024-03-08T03:09:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=66bd3cd75b32ccfa8d228c200cf4fbf72d49fd1f'/>
<id>66bd3cd75b32ccfa8d228c200cf4fbf72d49fd1f</id>
<content type='text'>
PR #75982 had been created before these tests were added, therefore
some test were not updated.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
PR #75982 had been created before these tests were added, therefore
some test were not updated.
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore "Implement convergence control in MIR using SelectionDAG (#71785)"</title>
<updated>2024-03-06T06:49:32+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2024-03-06T06:47:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=60822637bf007cbaf7401a6ec25cdf2ea7b7edbd'/>
<id>60822637bf007cbaf7401a6ec25cdf2ea7b7edbd</id>
<content type='text'>
This restores commit c7fdd8c11e54585dc9d15d63de9742067e0506b9.
Previously reverted in f010b1bef4dda2c7082cbb41dbabf1f149cce306.

LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This restores commit c7fdd8c11e54585dc9d15d63de9742067e0506b9.
Previously reverted in f010b1bef4dda2c7082cbb41dbabf1f149cce306.

LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Restore "Implement convergence control in MIR using SelectionDAG (#71785)""</title>
<updated>2024-03-04T16:05:34+00:00</updated>
<author>
<name>Mitch Phillips</name>
<email>mitchp@google.com</email>
</author>
<published>2024-03-04T16:04:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f010b1bef4dda2c7082cbb41dbabf1f149cce306'/>
<id>f010b1bef4dda2c7082cbb41dbabf1f149cce306</id>
<content type='text'>
This reverts commit c7fdd8c11e54585dc9d15d63de9742067e0506b9.

Reason: Broke the sanitizer buildbots. See the comments at
https://github.com/llvm/llvm-project/pull/71785
for more information.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit c7fdd8c11e54585dc9d15d63de9742067e0506b9.

Reason: Broke the sanitizer buildbots. See the comments at
https://github.com/llvm/llvm-project/pull/71785
for more information.
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore "Implement convergence control in MIR using SelectionDAG (#71785)"</title>
<updated>2024-03-04T07:58:04+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2024-03-04T06:01:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c7fdd8c11e54585dc9d15d63de9742067e0506b9'/>
<id>c7fdd8c11e54585dc9d15d63de9742067e0506b9</id>
<content type='text'>
Original commit 79889734b940356ab3381423c93ae06f22e772c9.
Perviously reverted in commit a2afcd5721869d1d03c8146bae3885b3385ba15e.

LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Original commit 79889734b940356ab3381423c93ae06f22e772c9.
Perviously reverted in commit a2afcd5721869d1d03c8146bae3885b3385ba15e.

LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Implement convergence control in MIR using SelectionDAG (#71785)"</title>
<updated>2024-02-21T05:37:02+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2024-02-21T05:37:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a2afcd5721869d1d03c8146bae3885b3385ba15e'/>
<id>a2afcd5721869d1d03c8146bae3885b3385ba15e</id>
<content type='text'>
This reverts commit 79889734b940356ab3381423c93ae06f22e772c9.

Encountered multiple buildbot failures.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 79889734b940356ab3381423c93ae06f22e772c9.

Encountered multiple buildbot failures.
</pre>
</div>
</content>
</entry>
<entry>
<title>Implement convergence control in MIR using SelectionDAG (#71785)</title>
<updated>2024-02-21T04:36:37+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2024-02-21T04:36:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=79889734b940356ab3381423c93ae06f22e772c9'/>
<id>79889734b940356ab3381423c93ae06f22e772c9</id>
<content type='text'>
LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
LLVM function calls carry convergence control tokens as operand bundles, where
the tokens themselves are produced by convergence control intrinsics. This patch
implements convergence control tokens in MIR as follows:

1. Introduce target-independent ISD opcodes and MIR opcodes for convergence
   control intrinsics.
2. Model token values as untyped virtual registers in MIR.

The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a
corresponding machine opcode with the same spelling. This glues the convergence
control token to SDNodes that represent calls to intrinsics. The glued token is
later translated to an implicit argument in the MIR.

The lowering of calls to user-defined functions is target-specific. On AMDGPU,
the convergence control operand bundle at a non-intrinsic call is translated to
an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment
converts this explicit argument to an implicit argument on the SI_CALL
instruction.</pre>
</div>
</content>
</entry>
</feed>
