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<title>llvm-project.git/llvm/test/CodeGen, branch users/mingmingl-llvm/spr/sdpglobalvariable</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Merge branch 'main' into users/mingmingl-llvm/spr/sdpglobalvariable</title>
<updated>2025-02-04T19:11:14+00:00</updated>
<author>
<name>mingmingl</name>
<email>mingmingl@google.com</email>
</author>
<published>2025-02-04T19:11:14+00:00</published>
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<entry>
<title>add test cases</title>
<updated>2025-02-04T18:46:52+00:00</updated>
<author>
<name>mingmingl</name>
<email>mingmingl@google.com</email>
</author>
<published>2025-02-04T18:46:52+00:00</published>
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<entry>
<title>GlobalISel: Fix defined register of invariant.start (#125664)</title>
<updated>2025-02-04T16:59:03+00:00</updated>
<author>
<name>Robert Imschweiler</name>
<email>50044286+ro-i@users.noreply.github.com</email>
</author>
<published>2025-02-04T16:59:03+00:00</published>
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<content type='text'>
In contrast to SelectionDAG, GlobalISel created a new virtual register
for the return value of invariant.start, leaving subsequent users of the
invariant.start value with an undefined reference.
A minimal example:
```
  %tmp = alloca i32, align 4, addrspace(5)
  %tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
  call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
  store i32 %i, ptr %tmpI, align 4
```
Although the return value of invariant.start might not be intended for
any use beyond invariant.end (the fuzzer might not have created a
sensible situation here), an implicit definition of the corresponding
virtual register avoids a segfault in the target instruction selector
later.

This LLVM defect was identified via the AMD Fuzzing project.</content>
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In contrast to SelectionDAG, GlobalISel created a new virtual register
for the return value of invariant.start, leaving subsequent users of the
invariant.start value with an undefined reference.
A minimal example:
```
  %tmp = alloca i32, align 4, addrspace(5)
  %tmpI = call ptr @llvm.invariant.start.p5(i64 4, ptr addrspace(5) %tmp) #3
  call void @llvm.invariant.end.p5(ptr %tmpI, i64 4, ptr addrspace(5) %tmp) #3
  store i32 %i, ptr %tmpI, align 4
```
Although the return value of invariant.start might not be intended for
any use beyond invariant.end (the fuzzer might not have created a
sensible situation here), an implicit definition of the corresponding
virtual register avoids a segfault in the target instruction selector
later.

This LLVM defect was identified via the AMD Fuzzing project.</pre>
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</entry>
<entry>
<title>[AArch64][SME] Extend FORM_TRANSPOSED pseudos to all multi-vector intrinsics (#124258)</title>
<updated>2025-02-04T16:28:06+00:00</updated>
<author>
<name>Kerry McLaughlin</name>
<email>kerry.mclaughlin@arm.com</email>
</author>
<published>2025-02-04T16:28:06+00:00</published>
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All patterns for multi-vector intrinsics should try to use the FORM_TRANSPOSED
pseudos so that they can benefit from register allocation hints when SME is available.

This patch removes the post-isel hook for the pseudo and instead extends the
SMEPeepholeOpt pass to replace a REG_SEQENCE with the pseudo if the
expected pattern of StridedOrContiguous copies is found. With this change,
the tablegen patterns for the intrinsics can remain unchanged.

One test has been added for each multiclass this affects.</content>
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All patterns for multi-vector intrinsics should try to use the FORM_TRANSPOSED
pseudos so that they can benefit from register allocation hints when SME is available.

This patch removes the post-isel hook for the pseudo and instead extends the
SMEPeepholeOpt pass to replace a REG_SEQENCE with the pseudo if the
expected pattern of StridedOrContiguous copies is found. With this change,
the tablegen patterns for the intrinsics can remain unchanged.

One test has been added for each multiclass this affects.</pre>
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</entry>
<entry>
<title>[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)</title>
<updated>2025-02-04T16:20:40+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-02-04T16:20:40+00:00</published>
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<id>5eff19f48b6493d52eeab74d9a81867d49f61bbb</id>
<content type='text'>
True16 codegen for FPtoi1.

It seems tablegen figured out the pattern even without this pat in
place, and the fptoui/fptosi.ll already got the right transformation.
Aditionally updated the mir file and split it to pre-gfx11 and
post-gfx11.</content>
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True16 codegen for FPtoi1.

It seems tablegen figured out the pattern even without this pat in
place, and the fptoui/fptosi.ll already got the right transformation.
Aditionally updated the mir file and split it to pre-gfx11 and
post-gfx11.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] true16 codegen for FPMinMax pat (#125107)</title>
<updated>2025-02-04T16:20:17+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-02-04T16:20:17+00:00</published>
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<id>6515fdf73de724d21b6c807ad75f2139c1d7af32</id>
<content type='text'>
true16 codegen for FPMinMax Pattern</content>
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true16 codegen for FPMinMax Pattern</pre>
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</entry>
<entry>
<title>[RISCV] Fold vector shift of sext/zext to widening multiply (#121563)</title>
<updated>2025-02-04T15:59:57+00:00</updated>
<author>
<name>Piotr Fusik</name>
<email>p.fusik@samsung.com</email>
</author>
<published>2025-02-04T15:59:57+00:00</published>
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<id>f7aad60cd1a538fb1eb5ab861f8c29ddba5283a4</id>
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    (shl (sext X), C) -&gt; (vwmulsu X, 1u &lt;&lt; C)
    (shl (zext X), C) -&gt; (vwmulu  X, 1u &lt;&lt; C)</content>
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<pre>
    (shl (sext X), C) -&gt; (vwmulsu X, 1u &lt;&lt; C)
    (shl (zext X), C) -&gt; (vwmulu  X, 1u &lt;&lt; C)</pre>
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</entry>
<entry>
<title>[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)</title>
<updated>2025-02-04T15:04:19+00:00</updated>
<author>
<name>Michael Maitland</name>
<email>michaeltmaitland@gmail.com</email>
</author>
<published>2025-02-04T15:04:19+00:00</published>
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<id>93b90a532d0ca5a95c226e3d0b37444ef692d3da</id>
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MBBFrameObjsReachingDefs was not being built correctly since we were not
inserting into a reference of Frame2InstrIdx. If there was multiple
stack slot defs in the same basic block, then the bug would occur. This
PR fixes this problem while simplifying the insertion logic.

Additionally, when lookup into MBBFrameObjsReachingDefs was occurring,
there was a chance that there was no entry in the map, in the case that
there was no reaching def. This was causing us to return a default
value, which may or may not have been correct. This patch returns the
correct value now.</content>
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<pre>
MBBFrameObjsReachingDefs was not being built correctly since we were not
inserting into a reference of Frame2InstrIdx. If there was multiple
stack slot defs in the same basic block, then the bug would occur. This
PR fixes this problem while simplifying the insertion logic.

Additionally, when lookup into MBBFrameObjsReachingDefs was occurring,
there was a chance that there was no entry in the map, in the case that
there was no reaching def. This was causing us to return a default
value, which may or may not have been correct. This patch returns the
correct value now.</pre>
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</content>
</entry>
<entry>
<title>[X86] avx512-load-store.ll - regenerate VMOVSD/VMOVSS comments</title>
<updated>2025-02-04T14:25:07+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-02-04T14:25:07+00:00</published>
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<entry>
<title>[X86] avx512-logic.ll - regenerate VPTERNLOG comments</title>
<updated>2025-02-04T14:21:11+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-02-04T14:11:15+00:00</published>
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