llvm-project.git/llvm/test/CodeGen, branch users/mingmingl-llvm/samplefdo-profile-format Unnamed repository; edit this file 'description' to name the repository. Revert "[DAGCombiner] Relax condition for extract_vector_elt combine" (#157953) 2025-09-10T21:33:44+00:00 Arthur Eubanks aeubanks@google.com 2025-09-10T21:33:44+00:00 984251acadb4b14bdb73b7a16fb0ccf134120c4b Reverts llvm/llvm-project#157658 Causes hangs, see https://github.com/llvm/llvm-project/pull/157658#issuecomment-3276441812 
Reverts llvm/llvm-project#157658

Causes hangs, see
https://github.com/llvm/llvm-project/pull/157658#issuecomment-3276441812
 [AMDGPU] NFC. Add testcase to test SIInsertWaitcnts::generateWaitcntInstBefore (#157938) 2025-09-10T20:39:02+00:00 choikwa 5455710+choikwa@users.noreply.github.com 2025-09-10T20:39:02+00:00 8ae3aeaca0b2de1702c90b120ef4b57accef9a3c Pre-commit testcase for https://github.com/llvm/llvm-project/pull/157821 
Pre-commit testcase for https://github.com/llvm/llvm-project/pull/157821
 [RISCV][GISel] Widen G_ABDS/G_ABDU before lowering when Zbb is enabled. (#157766) 2025-09-10T19:17:30+00:00 Craig Topper craig.topper@sifive.com 2025-09-10T19:17:30+00:00 262c7b7b5a996b0c46fdfc3480273f1864edc1c0 This allows us to use G_SMIN/SMAX/UMIN/UMAX in the lowering. 
This allows us to use G_SMIN/SMAX/UMIN/UMAX in the lowering.
 [DirectX] Removing dxbc DescriptorRange from mcbxdc (#154629) 2025-09-10T18:49:01+00:00 joaosaffran joaosaffranllvm@gmail.com 2025-09-10T18:49:01+00:00 9e778f6cd155f64896a9a0580e96aa4814ca999b MC Descriptor Range Representation currently depend on Object structures. This PR removes that dependency and in order to facilitate removing to_underlying usage in follow-up PRs. 
MC Descriptor Range Representation currently depend on Object
structures. This PR removes that dependency and in order to facilitate
removing to_underlying usage in follow-up PRs.
 [RISCV] Extend zvqdot matching to handle disjoint or (#157901) 2025-09-10T17:27:51+00:00 Hongyu Chen xxs_chy@outlook.com 2025-09-10T17:27:51+00:00 33c9236bf870bc732a48a0256e90b907d1c21a49 This patch makes use of pattern matching to handle disjoint or. Also, it simplifies the multiplication matching. 
This patch makes use of pattern matching to handle disjoint or. Also, it
simplifies the multiplication matching.
 [RISCV] Fold (X & -(1 << C1) & 0xffffffff) == C2 << C1 to sraiw X, C1 == C2. (#157617) 2025-09-10T15:51:47+00:00 Craig Topper craig.topper@sifive.com 2025-09-10T15:51:47+00:00 61e4d2312d59d059f775734a3a7c96a6914c07b7 We had an existing fold for (X & -(1 << C1) & 0xffffffff) == 0 which we can generalize to support comparing to constants other than 0. Previously we used srliw, but this generalizes better using sraiw. I'm restricting to the case where C2 is simm12 or 2048 to allow sraiw+addi/xori+seqz/snez to be used. Other constants require a more careful analysis of the constants involved. 
We had an existing fold for (X & -(1 << C1) & 0xffffffff) == 0
which we can generalize to support comparing to constants other
than 0.
    
Previously we used srliw, but this generalizes better using sraiw.
I'm restricting to the case where C2 is simm12 or 2048 to allow
sraiw+addi/xori+seqz/snez to be used. Other constants require a
more careful analysis of the constants involved.
 [AMDGPU] Propagate Constants for Wave Reduction Intrinsics (#150395) 2025-09-10T14:43:30+00:00 Aaditya 115080342+easyonaadit@users.noreply.github.com 2025-09-10T14:43:30+00:00 bdebbd90150fbba210c097188e49b51d0eb960a4 






[GISel] Combine shift + trunc + shift pattern (#155583)
2025-09-10T14:01:55+00:00

jyli0116
yu.li@arm.com

2025-09-10T14:01:55+00:00

619d36ff4f7552b0e5786f4cf24d93d8b881aa58

Folds shift(trunc(shift(...))) pattern into trunc(shift(...)) by
combining the two shift instructions




Folds shift(trunc(shift(...))) pattern into trunc(shift(...)) by
combining the two shift instructions






[AMDGPU] Extending wave reduction intrinsics for `i64` types - 3 (#151310)
2025-09-10T13:34:24+00:00

Aaditya
115080342+easyonaadit@users.noreply.github.com

2025-09-10T13:34:24+00:00

1e6a63e4fff4a496c537e5c155af8b355d3a988c

Supporting Arithemtic Operations: `and`, `or`, `xor`




Supporting Arithemtic Operations: `and`, `or`, `xor`






[AMDGPU] Generate canonical additions in AMDGPUPromoteAlloca (#157810)
2025-09-10T12:46:46+00:00

Fabian Ritter
fabian.ritter@amd.com

2025-09-10T12:46:46+00:00

5b81367960e71d40b948f433664790ec8a19f224

When we know that one operand of an addition is a constant, we might was
well put it on the right-hand side and avoid the work to canonicalize it
in a later pass.




When we know that one operand of an addition is a constant, we might was
well put it on the right-hand side and avoid the work to canonicalize it
in a later pass.