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<title>llvm-project.git/llvm/test/CodeGen/X86, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[X86] fp128-select.ll - remove CFI noise</title>
<updated>2025-07-03T12:14:59+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-03T12:13:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=791bb606b5bd5b7710fc516e8ed8855e1257f186'/>
<id>791bb606b5bd5b7710fc516e8ed8855e1257f186</id>
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</content>
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<pre>
</pre>
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<entry>
<title>[PHIElimination] Revert #131837 #146320 #146337 (#146850)</title>
<updated>2025-07-03T11:48:08+00:00</updated>
<author>
<name>Guy David</name>
<email>49722543+guy-david@users.noreply.github.com</email>
</author>
<published>2025-07-03T11:48:08+00:00</published>
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<id>76274eb2b3439aac6991c6b505248e00627e5693</id>
<content type='text'>
Reverting because mis-compiles:
- https://github.com/llvm/llvm-project/pull/131837
- https://github.com/llvm/llvm-project/pull/146320
- https://github.com/llvm/llvm-project/pull/146337</content>
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<pre>
Reverting because mis-compiles:
- https://github.com/llvm/llvm-project/pull/131837
- https://github.com/llvm/llvm-project/pull/146320
- https://github.com/llvm/llvm-project/pull/146337</pre>
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</content>
</entry>
<entry>
<title>[X86] Add BLEND/UNPCK shuffles to canCreateUndefOrPoisonForTargetNode/isGuaranteedNotToBeUndefOrPoisonForTargetNode (#146728)</title>
<updated>2025-07-02T17:38:00+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-02T17:38:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=aa8e1bc0e9892ddbd84333767f71dc191cc10140'/>
<id>aa8e1bc0e9892ddbd84333767f71dc191cc10140</id>
<content type='text'>
None of these implicitly generate UNDEF/POISON</content>
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<pre>
None of these implicitly generate UNDEF/POISON</pre>
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</content>
</entry>
<entry>
<title>[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)</title>
<updated>2025-07-02T16:44:54+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-07-02T16:44:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b62826cc054cfff75f2b5c83b980f1e12fc25e3a'/>
<id>b62826cc054cfff75f2b5c83b980f1e12fc25e3a</id>
<content type='text'>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</content>
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<pre>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</pre>
</div>
</content>
</entry>
<entry>
<title>[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)</title>
<updated>2025-07-02T14:07:48+00:00</updated>
<author>
<name>woruyu</name>
<email>99597449+woruyu@users.noreply.github.com</email>
</author>
<published>2025-07-02T14:07:48+00:00</published>
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<id>bbcebec3af5ac473f5d3557683f18a79a4b12ab5</id>
<content type='text'>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</content>
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<pre>
This PR resolves https://github.com/llvm/llvm-project/issues/144513

The modification include five pattern :
1.vselect Cond, 0, 0 → 0
2.vselect Cond, -1, 0 → bitcast Cond
3.vselect Cond, -1, x → or Cond, x
4.vselect Cond, x, 0 → and Cond, x
5.vselect Cond, 000..., X -&gt; andn Cond, X

1-4 have been migrated to DAGCombine. 5 still in x86 code.

The reason is that you cannot use the andn instruction directly in
DAGCombine, you can only use and+xor, which will introduce optimization
order issues. For example, in the x86 backend, select Cond, 0, x →
(~Cond) &amp; x, the backend will first check whether the cond node of
(~Cond) is a setcc node. If so, it will modify the comparison operator
of the condition.So the x86 backend cannot complete the optimization of
andn.In short, I think it is a better choice to keep the pattern of
vselect Cond, 000..., X instead of and+xor in combineDAG.

For commit, the first is code changes and x86 test(note 1), the second
is tests in other backend(node 2).

---------

Co-authored-by: Simon Pilgrim &lt;llvm-dev@redking.me.uk&gt;</pre>
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</content>
</entry>
<entry>
<title>[DAG] visitFREEZE - always allow freezing multiple operands (#145939)</title>
<updated>2025-07-02T10:28:37+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-02T10:28:37+00:00</published>
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<id>38200e94f1428b586dc1778133120541e65c20b5</id>
<content type='text'>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</content>
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<pre>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</pre>
</div>
</content>
</entry>
<entry>
<title>[SelectionDAG] Fix NaN regression in fma dag-combine. (#146592)</title>
<updated>2025-07-01T22:10:30+00:00</updated>
<author>
<name>James Y Knight</name>
<email>jyknight@google.com</email>
</author>
<published>2025-07-01T22:10:30+00:00</published>
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<id>ae2104897c7d9f887c415b07fb2662486082b248</id>
<content type='text'>
After 901e1390c9778a191256335d37802bc631c2d183 (#127770), the DAG
combine would transform `fma(x, 0.0, 1.0)` into `1.0` if
`-fp-contract=fast` was enabled, in addition to when 'x' is marked
nnan/ninf.

It's only valid in the latter case, not the former, so delete the extra
condition.</content>
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<pre>
After 901e1390c9778a191256335d37802bc631c2d183 (#127770), the DAG
combine would transform `fma(x, 0.0, 1.0)` into `1.0` if
`-fp-contract=fast` was enabled, in addition to when 'x' is marked
nnan/ninf.

It's only valid in the latter case, not the former, so delete the extra
condition.</pre>
</div>
</content>
</entry>
<entry>
<title>[X86] freeze-vector.ll - fix cut+pasta typo in frozen build vector tests</title>
<updated>2025-07-01T16:36:43+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T16:35:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b697b801b13d94aa88f19a9f7dc7197b1f658186'/>
<id>b697b801b13d94aa88f19a9f7dc7197b1f658186</id>
<content type='text'>
Ensure we load BOTH scalars, inserted into different positions into separate vectors with the freeze(poison) base

Noticed while triaging regressions in #145939
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<pre>
Ensure we load BOTH scalars, inserted into different positions into separate vectors with the freeze(poison) base

Noticed while triaging regressions in #145939
</pre>
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</content>
</entry>
<entry>
<title>[X86] legalize-sub-zero.ll - regenerate test checks</title>
<updated>2025-07-01T15:07:32+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T14:59:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6b1c92cbcb760ff95affc66c689236d40288e1ad'/>
<id>6b1c92cbcb760ff95affc66c689236d40288e1ad</id>
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</pre>
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</entry>
<entry>
<title>[DAG] canCreateUndefOrPoison - add handling for CTTZ/CTLZ_ZERO_UNDEF nodes (#146501)</title>
<updated>2025-07-01T11:44:45+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-01T11:44:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=56841565db77af6eb668b59add3cb1d0f38875e8'/>
<id>56841565db77af6eb668b59add3cb1d0f38875e8</id>
<content type='text'>
CTTZ/CTLZ_ZERO_UNDEF nodes can only create poison if the source value is zero - so check with isKnownNeverZero

Pulled out of #146361 and reapplied now that #146490 has landed.</content>
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<pre>
CTTZ/CTLZ_ZERO_UNDEF nodes can only create poison if the source value is zero - so check with isKnownNeverZero

Pulled out of #146361 and reapplied now that #146490 has landed.</pre>
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