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<title>llvm-project.git/llvm/test/CodeGen/X86/bfloat.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)</title>
<updated>2025-04-22T21:36:41+00:00</updated>
<author>
<name>zhijian lin</name>
<email>zhijian@ca.ibm.com</email>
</author>
<published>2025-04-22T21:36:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=afda4c295b1f8c4c4011358eddc1a08e17cd5b4d'/>
<id>afda4c295b1f8c4c4011358eddc1a08e17cd5b4d</id>
<content type='text'>
This patch addresses the signed/zero extension of poison by using a
poison value of the extended type instead of a constant zero of the
extended type.</content>
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<pre>
This patch addresses the signed/zero extension of poison by using a
poison value of the extended type instead of a constant zero of the
extended type.</pre>
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</content>
</entry>
<entry>
<title>[X86] Add test coverage for bfloat &lt;-&gt; half conversion</title>
<updated>2025-02-18T16:49:51+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-02-18T16:08:36+00:00</published>
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<id>bfcec1999c7ec30c53ccfcda372a4e9e27a43268</id>
<content type='text'>
Inspired by #90738 (although that is a clang codegen issue)
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<pre>
Inspired by #90738 (although that is a clang codegen issue)
</pre>
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</content>
</entry>
<entry>
<title>[X86] Fold (f16 bitcast extract_vectorelt(v,0)) to (extract_vectorelt (v8f16 bitcast(v,0))) (#125877)</title>
<updated>2025-02-06T08:29:39+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-02-06T08:29:39+00:00</published>
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<id>f82902fef4a004a7f26d49448e66b2dbeed4d692</id>
<content type='text'>
Also handles possible truncations from i32 to i16.

Cleans up some of the poor codegen identified in #98630</content>
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<pre>
Also handles possible truncations from i32 to i16.

Cleans up some of the poor codegen identified in #98630</pre>
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</content>
</entry>
<entry>
<title>[X86] Fold (v4i32 (scalar_to_vector (i32 (anyext (bitcast (f16)))))) -&gt; (v4i32 bitcast (v8f16 scalar_to_vector)) (#123338)</title>
<updated>2025-01-17T14:46:22+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-01-17T14:46:22+00:00</published>
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<id>76569025dd8b026b3309dedbcaf877d16eace805</id>
<content type='text'>
This pattern tends to appear during f16 -&gt; f32 promotion

Partially addresses the unnecessary XMM-&gt;GPR-&gt;XMM moves when working with f16 types (#107086)</content>
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<pre>
This pattern tends to appear during f16 -&gt; f32 promotion

Partially addresses the unnecessary XMM-&gt;GPR-&gt;XMM moves when working with f16 types (#107086)</pre>
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</content>
</entry>
<entry>
<title>[LegalizeTypes][RISCV][X86] Legalize FP_ROUND to libcall in SoftPromoteHalfRes_FP_ROUND if the input type is softened. (#119481)</title>
<updated>2024-12-11T06:21:49+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2024-12-11T06:21:49+00:00</published>
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<id>839c8217b989a22908fdd1ec48105ff22d655fb2</id>
<content type='text'>
Previously we created an FP_TO_FP16 and legalized it in
SoftenFloatOp_FP_ROUND. This caused i16 to be sent to call lowering
instead of f16. This results in the ABI not being followed if f16 is
supposed to be passed in a different register than i16.

Looking at the libgcc binary for the library function it appears the value
is returned in xmm0 so the X86 test was being miscompiled before.

Fixes #107607.</content>
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<pre>
Previously we created an FP_TO_FP16 and legalized it in
SoftenFloatOp_FP_ROUND. This caused i16 to be sent to call lowering
instead of f16. This results in the ABI not being followed if f16 is
supposed to be passed in a different register than i16.

Looking at the libgcc binary for the library function it appears the value
is returned in xmm0 so the X86 test was being miscompiled before.

Fixes #107607.</pre>
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</content>
</entry>
<entry>
<title>[X86][BF16] Add libcall for FP128 -&gt; BF16 (#115825)</title>
<updated>2024-11-12T07:54:09+00:00</updated>
<author>
<name>Feng Zou</name>
<email>feng.zou@intel.com</email>
</author>
<published>2024-11-12T07:54:09+00:00</published>
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<id>28e4aad45a64ec893c02f21b9c2afe7efe5f4a2a</id>
<content type='text'>
This is to fix #115710.</content>
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<pre>
This is to fix #115710.</pre>
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</content>
</entry>
<entry>
<title>Reland "[X86][BF16] Add libcall for F80 -&gt; BF16 (#109116)" (#109143)</title>
<updated>2024-09-19T07:39:07+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-09-19T07:39:07+00:00</published>
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<id>c18be32185ca10e55bdef0f2d43629ccfb7e89eb</id>
<content type='text'>
This reverts commit ababfee78714313a0cad87591b819f0944b90d09.

Add X86 FP80 check.</content>
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<pre>
This reverts commit ababfee78714313a0cad87591b819f0944b90d09.

Add X86 FP80 check.</pre>
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</content>
</entry>
<entry>
<title>Revert "[X86][BF16] Add libcall for F80 -&gt; BF16" (#109140)</title>
<updated>2024-09-18T13:35:38+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-09-18T13:35:38+00:00</published>
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<id>a10c9f994be143e2ac63918aa495bc2aeb3ffb48</id>
<content type='text'>
Reverts llvm/llvm-project#109116</content>
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<pre>
Reverts llvm/llvm-project#109116</pre>
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</content>
</entry>
<entry>
<title>[X86][BF16] Add libcall for F80 -&gt; BF16 (#109116)</title>
<updated>2024-09-18T13:23:10+00:00</updated>
<author>
<name>Phoebe Wang</name>
<email>phoebe.wang@intel.com</email>
</author>
<published>2024-09-18T13:23:10+00:00</published>
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<id>76eda76f9f36646b8b393f2369359d02e24e20c8</id>
<content type='text'>
This fixes #108936, but the calling convention doesn't match with GCC. I
doubt we have such a lib function for now, so leave the calling
convention as is.</content>
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<pre>
This fixes #108936, but the calling convention doesn't match with GCC. I
doubt we have such a lib function for now, so leave the calling
convention as is.</pre>
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</content>
</entry>
<entry>
<title>[ScalarizeMaskedMemIntr] Optimize splat non-constant masks (#104537)</title>
<updated>2024-08-16T21:24:25+00:00</updated>
<author>
<name>Krzysztof Drewniak</name>
<email>Krzysztof.Drewniak@amd.com</email>
</author>
<published>2024-08-16T21:24:25+00:00</published>
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<id>70995a1a3379ed3c21b1c5da6723f04166cb0ae6</id>
<content type='text'>
In cases (like the ones added in the tests) where the condition of a
masked load or store is a splat but not a constant (that is, a masked
operation is being used to implement patterns like "load if the current
lane is in-bounds, otherwise return 0"), optimize the 'scalarized' code
to perform an aligned vector load/store if the splat constant is true.

Additionally, take a few steps to preserve aliasing information and
names when nothing is scalarized while I'm here.

As motivation, some LLVM IR users will genatate masked load/store in
cases that map to this kind of predicated operation (where either the
vector is loaded/stored or it isn't) in order to take advantage of
hardware primitives, but on AMDGPU, where we don't have a masked load or
store, this pass would scalarize a load or store that was intended to be
- and can be - vectorized while also introducing expensive branches.

Fixes #104520

Pre-commit tests at #104527</content>
<content type='xhtml'>
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<pre>
In cases (like the ones added in the tests) where the condition of a
masked load or store is a splat but not a constant (that is, a masked
operation is being used to implement patterns like "load if the current
lane is in-bounds, otherwise return 0"), optimize the 'scalarized' code
to perform an aligned vector load/store if the splat constant is true.

Additionally, take a few steps to preserve aliasing information and
names when nothing is scalarized while I'm here.

As motivation, some LLVM IR users will genatate masked load/store in
cases that map to this kind of predicated operation (where either the
vector is loaded/stored or it isn't) in order to take advantage of
hardware primitives, but on AMDGPU, where we don't have a masked load or
store, this pass would scalarize a load or store that was intended to be
- and can be - vectorized while also introducing expensive branches.

Fixes #104520

Pre-commit tests at #104527</pre>
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</content>
</entry>
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