llvm-project.git/llvm/test/CodeGen/WebAssembly/vector-reduce.ll, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [WebAssembly] Ofast pmin/pmax pattern matchers (#100107) 2024-07-24T08:23:49+00:00 Sam Parker sam.parker@arm.com 2024-07-24T08:23:49+00:00 a3de21cac1fb8f1dd98cfe1d1443e2d3f0a97351 With fast-math, the ordered setcc nodes are converted to setcc nodes which do not care about NaNs, so add patterns that use setlt, setle, setgt and setge. 
With fast-math, the ordered setcc nodes are converted to setcc nodes
which do not care about NaNs, so add patterns that use setlt, setle,
setgt and setge.
 [TTI][WebAssembly] Pairwise reduction expansion (#93948) 2024-07-17T08:21:52+00:00 Sam Parker sam.parker@arm.com 2024-07-17T08:21:52+00:00 d28ed29d6bd9f0389092775406fff7e6205d4d5f WebAssembly doesn't support horizontal operations nor does it have a way of expressing fast-math or reassoc flags, so runtimes are currently unable to use pairwise operations when generating code from the existing shuffle patterns. This patch allows the backend to select which, arbitary, shuffle pattern to be used per reduction intrinsic. The default behaviour is the same as the existing, which is by splitting the vector into a top and bottom half. The other pattern introduced is for a pairwise shuffle. WebAssembly enables pairwise reductions for int/fp add/sub. 
WebAssembly doesn't support horizontal operations nor does it have a way
of expressing fast-math or reassoc flags, so runtimes are currently
unable to use pairwise operations when generating code from the existing
shuffle patterns.

This patch allows the backend to select which, arbitary, shuffle pattern
to be used per reduction intrinsic. The default behaviour is the same as
the existing, which is by splitting the vector into a top and bottom
half. The other pattern introduced is for a pairwise shuffle.

WebAssembly enables pairwise reductions for int/fp add/sub.