llvm-project.git/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll, branch users/nico/python-2

[WebAssembly] Fix assertion in LowerBUILD_VECTOR (#101961)

2024-08-05T21:38:12+00:00

The assertion was failing in the case where we were trying to lower to
loadxx_zero, but lane zero was undef.

[WebAssembly] load_zero to initialise build_vector (#100610)

2024-08-02T09:11:21+00:00

Instead of splatting a single lane, to initialise a build_vector, lower
to scalar_to_vector which can be selected to load_zero.

Also add load_zero and load_lane patterns for f32x4 and f64x2.

[WebAssembly] Replace LOAD_SPLAT with SPLAT_VECTOR

2023-01-04T15:07:47+00:00

Splats were selected by matching on uses of `build_vector` with
identical elements, but a while back a target independent node for
vector splatting was added.
This removes the WebAssembly specific LOAD_SPLAT intrinsic, and instead
makes SPLAT_VECTOR legal and adds patterns for splat loads.

Differential Revision: https://reviews.llvm.org/D139871

[CodeGen] Using ZExt for extractelement indices.

2022-10-15T22:45:35+00:00

In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978

[WebAssembly] Improve codegen for shuffles with undefined lane indices

2022-09-13T23:03:18+00:00

For undefined lane indices, fill the mask with {0..N} instead of zeros to allow
further reduction to word/dword shuffle on the VM.

Reviewed By: tlively, penzn

Differential Revision: https://reviews.llvm.org/D133473

[WebAssembly] Regenerate simd-build-vector.ll to show full codegen

2022-06-08T15:54:26+00:00

[WebAssembly] Codegen for v128.loadX_lane instructions

2021-07-14T18:31:53+00:00

Replace the experimental clang builtin and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50433.

Differential Revision: https://reviews.llvm.org/D105950

[WebAssembly] Remove datalayout strings from llc tests

2021-07-14T18:17:08+00:00

The data layout strings do not have any effect on llc tests and will become
misleadingly out of date as we continue to update the canonical data layout, so
remove them from the tests.

Differential Revision: https://reviews.llvm.org/D105842

[WebAssembly] Add shuffles as an option for lowering BUILD_VECTOR

2021-04-09T18:21:49+00:00

When lowering a BUILD_VECTOR SDNode, we choose among various possible vector
creation instructions in an attempt to minimize the total number of instructions
used. We previously considered using swizzles, consts, and splats, and this
patch adds shuffles as well. A common pattern that now lowers to shuffles is
when two 64-bit vectors are concatenated. Previously, concatenations generally
lowered to sequences of extract_lane and replace_lane instructions when they
could have been a single shuffle.

Differential Revision: https://reviews.llvm.org/D100018

[WebAssembly] Remove unimplemented-simd target feature

2021-03-18T17:23:12+00:00

Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature for gating
SIMD instructions that engines have not implemented. With this change,
v128.const is now enabled by default with the simd128 target feature.

Differential Revision: https://reviews.llvm.org/D98457