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<title>llvm-project.git/llvm/test/CodeGen/SystemZ/vec-sext.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[DAGTypeLegalizer] Handle SIGN/ZERO_EXTEND in WidenVecRes_Convert().</title>
<updated>2017-01-27T07:46:26+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2017-01-27T07:46:26+00:00</published>
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<id>bb0ed3e732aff72f44ef76733fdf79c043cbb5b9</id>
<content type='text'>
In case of a SIGN/ZERO_EXTEND of an incomplete vector type (using only a
partial number of available vector elements), WidenVecRes_Convert() used to
resort to scalarization.

This patch adds a handling of the (common) case where an input vector can be
found of same width as the widened result vector, by converting the node to
SIGN/ZERO_EXTEND_VECTOR_INREG.

Review: Eli Friedman
llvm-svn: 293268
</content>
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<pre>
In case of a SIGN/ZERO_EXTEND of an incomplete vector type (using only a
partial number of available vector elements), WidenVecRes_Convert() used to
resort to scalarization.

This patch adds a handling of the (common) case where an input vector can be
found of same width as the widened result vector, by converting the node to
SIGN/ZERO_EXTEND_VECTOR_INREG.

Review: Eli Friedman
llvm-svn: 293268
</pre>
</div>
</content>
</entry>
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