<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm-project.git/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[SystemZ] Optimize vector zero/sign extensions</title>
<updated>2025-03-15T17:28:44+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2025-03-15T17:14:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4a4987be360ac7e4caad65bed54de4ed1d9342ed'/>
<id>4a4987be360ac7e4caad65bed54de4ed1d9342ed</id>
<content type='text'>
Generate more efficient code for zero or sign extensions where
the source is a subvector generated via SHUFFLE_VECTOR.

Specifically, recognize patterns corresponding to (series of)
VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO
DOUBLEWORD instruction.

As a special case, also handle zero or sign extensions of a
vector element to i128.

Fixes: https://github.com/llvm/llvm-project/issues/129576
Fixes: https://github.com/llvm/llvm-project/issues/129899
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Generate more efficient code for zero or sign extensions where
the source is a subvector generated via SHUFFLE_VECTOR.

Specifically, recognize patterns corresponding to (series of)
VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO
DOUBLEWORD instruction.

As a special case, also handle zero or sign extensions of a
vector element to i128.

Fixes: https://github.com/llvm/llvm-project/issues/129576
Fixes: https://github.com/llvm/llvm-project/issues/129899
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Improve decoding in case of instructions with four register operands.</title>
<updated>2018-07-31T13:00:42+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2018-07-31T13:00:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2f12e45d5ae1adbc2b45f11191d0db6a0f8352b9'/>
<id>2f12e45d5ae1adbc2b45f11191d0db6a0f8352b9</id>
<content type='text'>
Since z13, the max group size will be 2 if any μop has more than 3 register
sources.

This has been ignored sofar in the SystemZHazardRecognizer, but is now
handled by recognizing those instructions and adjusting the tracking of
decoding and the cost heuristic for grouping.

Review: Ulrich Weigand
https://reviews.llvm.org/D49847

llvm-svn: 338368
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since z13, the max group size will be 2 if any μop has more than 3 register
sources.

This has been ignored sofar in the SystemZHazardRecognizer, but is now
handled by recognizing those instructions and adjusting the tracking of
decoding and the cost heuristic for grouping.

Review: Ulrich Weigand
https://reviews.llvm.org/D49847

llvm-svn: 338368
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings.</title>
<updated>2018-07-20T09:40:43+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2018-07-20T09:40:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c88d3f6a992a69c88aaccf06f5f8dc0fec0943f9'/>
<id>c88d3f6a992a69c88aaccf06f5f8dc0fec0943f9</id>
<content type='text'>
As a consequence of recent discussions
(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patch
changes the SystemZ SchedModels so that the IssueWidth is 6, which is the
decoder capacity, and NumMicroOps become the number of decoder slots needed
per instruction.

In addition, the SchedWrite latencies now match the MachineInstructions
def-operand indexes, and ReadAdvances have been added on instructions with
one register operand and one memory operand.

Review: Ulrich Weigand
https://reviews.llvm.org/D47008

llvm-svn: 337538
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As a consequence of recent discussions
(http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patch
changes the SystemZ SchedModels so that the IssueWidth is 6, which is the
decoder capacity, and NumMicroOps become the number of decoder slots needed
per instruction.

In addition, the SchedWrite latencies now match the MachineInstructions
def-operand indexes, and ReadAdvances have been added on instructions with
one register operand and one memory operand.

Review: Ulrich Weigand
https://reviews.llvm.org/D47008

llvm-svn: 337538
</pre>
</div>
</content>
</entry>
<entry>
<title>[CodeGen] Unify MBB reference format in both MIR and debug output</title>
<updated>2017-12-04T17:18:51+00:00</updated>
<author>
<name>Francis Visoiu Mistrih</name>
<email>francisvm@yahoo.com</email>
</author>
<published>2017-12-04T17:18:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=25528d6de70e98683722e28655d8568d5f09b5c7'/>
<id>25528d6de70e98683722e28655d8568d5f09b5c7</id>
<content type='text'>
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" &lt;&lt; ([a-zA-Z0-9_]+)-&gt;getNumber\(\)/" &lt;&lt; printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" &lt;&lt; ([a-zA-Z0-9_]+)\.getNumber\(\)/" &lt;&lt; printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" &lt;&lt; ([a-zA-Z0-9_]+)-&gt;getNumber\(\)/" &lt;&lt; printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" &lt;&lt; ([a-zA-Z0-9_]+)\.getNumber\(\)/" &lt;&lt; printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ]  Enable machine scheduler.</title>
<updated>2017-10-06T13:59:28+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2017-10-06T13:59:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c63ed222b8b2dd9ad83005b8378c184840b052d8'/>
<id>c63ed222b8b2dd9ad83005b8378c184840b052d8</id>
<content type='text'>
The machine scheduler (before register allocation) is enabled by default for
SystemZ.

The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).

Review: Ulrich Weigand
https://reviews.llvm.org/D37977

llvm-svn: 315063
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The machine scheduler (before register allocation) is enabled by default for
SystemZ.

The SelectionDAG scheduling preference now becomes source order scheduling
(was regpressure).

Review: Ulrich Weigand
https://reviews.llvm.org/D37977

llvm-svn: 315063
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ]  New CodeGen tests for vector compare / select.</title>
<updated>2017-03-17T07:11:46+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulsson@linux.vnet.ibm.com</email>
</author>
<published>2017-03-17T07:11:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=f496bd9a5931b59c68c16baee66606871e91c917'/>
<id>f496bd9a5931b59c68c16baee66606871e91c917</id>
<content type='text'>
New SystemZ tests for the improved codegen of vector compare and select,
including cases with a logical combination of two compares.

Review: Ulrich Weigand.
https://reviews.llvm.org/D29489

llvm-svn: 298049
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
New SystemZ tests for the improved codegen of vector compare and select,
including cases with a logical combination of two compares.

Review: Ulrich Weigand.
https://reviews.llvm.org/D29489

llvm-svn: 298049
</pre>
</div>
</content>
</entry>
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