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<title>llvm-project.git/llvm/test/CodeGen/SystemZ/stackmap.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/'/>
<entry>
<title>[SystemZ] Add support for 16-bit floating point. (#109164)</title>
<updated>2025-04-16T18:02:56+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2025-04-16T18:02:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6d03f51f0c59171f1ec3c5cc5c1fe71c30956273'/>
<id>6d03f51f0c59171f1ec3c5cc5c1fe71c30956273</id>
<content type='text'>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- _Float16 is now accepted by Clang.

- The half IR type is fully handled by the backend.

- These values are passed in FP registers and converted to/from float around
  each operation.

- Compiler-rt conversion functions are now built for s390x including the missing
  extendhfdf2 which was added.

Fixes #50374</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Enable MachineCombiner for FP reassociation (#83546)</title>
<updated>2024-04-30T15:09:54+00:00</updated>
<author>
<name>Jonas Paulsson</name>
<email>paulson1@linux.ibm.com</email>
</author>
<published>2024-04-30T15:09:54+00:00</published>
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<id>6c32a1fdf712e58a324fc0f6e3dfc83ed7d56b1e</id>
<content type='text'>
Enable MachineCombining for FP add, sub and mul.

In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.
</content>
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<pre>
Enable MachineCombining for FP add, sub and mul.

In order for this to work, the default instruction selection of reg/mem opcodes is disabled for ISD nodes that carry the flags that allow reassociation. The reg/mem folding is instead done after MachineCombiner by PeepholeOptimizer. SystemZInstrInfo optimizeLoadInstr() and foldMemoryOperandImpl() ("LoadMI version") have been implemented for this purpose also by this patch.
</pre>
</div>
</content>
</entry>
<entry>
<title>Migrate llvm.experimental.patchpoint() to ptr.</title>
<updated>2022-08-10T12:18:02+00:00</updated>
<author>
<name>Edd Barrett</name>
<email>vext01@gmail.com</email>
</author>
<published>2022-08-10T12:13:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fa250250b2966613fba7b88575029eb7cf0da66c'/>
<id>fa250250b2966613fba7b88575029eb7cf0da66c</id>
<content type='text'>
This intrinsic used a typed pointer for a call target operand. This
change updates the operand to be an opaque pointer and updates all
pointers in all test files that use the intrinsic.

Differential revision: https://reviews.llvm.org/D131261
</content>
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<pre>
This intrinsic used a typed pointer for a call target operand. This
change updates the operand to be an opaque pointer and updates all
pointers in all test files that use the intrinsic.

Differential revision: https://reviews.llvm.org/D131261
</pre>
</div>
</content>
</entry>
<entry>
<title>[stackmaps] Legalise patchpoint arguments.</title>
<updated>2022-07-15T11:01:59+00:00</updated>
<author>
<name>Edd Barrett</name>
<email>vext01@gmail.com</email>
</author>
<published>2022-07-15T11:00:14+00:00</published>
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<id>2e62a26fd77d5c63c27597609628251338ff13dc</id>
<content type='text'>
This is similar to D125680, but for llvm.experimental.patchpoint
(instead of llvm.experimental.stackmap).

Differential review: https://reviews.llvm.org/D129268
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is similar to D125680, but for llvm.experimental.patchpoint
(instead of llvm.experimental.stackmap).

Differential review: https://reviews.llvm.org/D129268
</pre>
</div>
</content>
</entry>
<entry>
<title>Test stackmap support for floating point types.</title>
<updated>2022-05-30T09:49:32+00:00</updated>
<author>
<name>Edd Barrett</name>
<email>vext01@gmail.com</email>
</author>
<published>2022-05-30T09:18:22+00:00</published>
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<id>d245974e1a7809f40d994548b46b4694f247fc99</id>
<content type='text'>
It appears that float support is complete, or at least, the stackmap records
emitted are not inconceivable (I must admit that I don't know about many of the
architectures under test here).

One curiosity, the SystemZ tests highlight an undocumented (or maybe incorrect)
quirk of the stackmap format: in the case of a Register record, the Offset or
SmallConstant field can encode a sub-register index! I've only ever seen this
field zero for Register entries up until now.
</content>
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<pre>
It appears that float support is complete, or at least, the stackmap records
emitted are not inconceivable (I must admit that I don't know about many of the
architectures under test here).

One curiosity, the SystemZ tests highlight an undocumented (or maybe incorrect)
quirk of the stackmap format: in the case of a Register record, the Offset or
SmallConstant field can encode a sub-register index! I've only ever seen this
field zero for Register entries up until now.
</pre>
</div>
</content>
</entry>
<entry>
<title>Test stackmap support for i128</title>
<updated>2022-05-23T10:56:24+00:00</updated>
<author>
<name>Edd Barrett</name>
<email>vext01@gmail.com</email>
</author>
<published>2022-05-23T10:18:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=c5e5cf12583895396269f2a56c78e4464bd143da'/>
<id>c5e5cf12583895396269f2a56c78e4464bd143da</id>
<content type='text'>
This diff adds tests that check the currently-working stackmap cases for i128.
This will help ensure no regressions are later introduced by D125680 (when
ready).

Note that i128 stackmap support is currently incomplete, so we cant test all
i128 functionality:

    i128 constants &gt;= 2^{63} crash LLVM
    non-constant i128s crash LLVM

So this change tests only constant i128 operands of value &lt; 2^{63}.

A couple of incorrect comments are also fixed.
</content>
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<pre>
This diff adds tests that check the currently-working stackmap cases for i128.
This will help ensure no regressions are later introduced by D125680 (when
ready).

Note that i128 stackmap support is currently incomplete, so we cant test all
i128 functionality:

    i128 constants &gt;= 2^{63} crash LLVM
    non-constant i128s crash LLVM

So this change tests only constant i128 operands of value &lt; 2^{63}.

A couple of incorrect comments are also fixed.
</pre>
</div>
</content>
</entry>
<entry>
<title>[SystemZ] Support stackmaps and patchpoints</title>
<updated>2018-03-02T20:39:30+00:00</updated>
<author>
<name>Ulrich Weigand</name>
<email>ulrich.weigand@de.ibm.com</email>
</author>
<published>2018-03-02T20:39:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5eb64110d241cf2506f54ade3c2693beed42dd8f'/>
<id>5eb64110d241cf2506f54ade3c2693beed42dd8f</id>
<content type='text'>
This adds back-end support for the @llvm.experimental.stackmap and
@llvm.experimental.patchpoint intrinsics.

llvm-svn: 326611
</content>
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<pre>
This adds back-end support for the @llvm.experimental.stackmap and
@llvm.experimental.patchpoint intrinsics.

llvm-svn: 326611
</pre>
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</content>
</entry>
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