llvm-project.git/llvm/test/CodeGen/SystemZ/debuginstr-02.mir, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [NewPM][CodeGen] Port `finalize-isel` to new pass manager (#94214) 2024-06-04T01:23:52+00:00 paperchalice liujunchang97@outlook.com 2024-06-04T01:23:52+00:00 9b0e1c2ca25be58ea29b318d3515e6171f25f0ea It should preserve more analysis results, but it happens immediately after instruction selection. 
It should preserve more analysis results, but it happens immediately
after instruction selection.
 [SystemZ] Improve emitSelect() 2019-09-25T14:00:33+00:00 Jonas Paulsson paulsson@linux.vnet.ibm.com 2019-09-25T14:00:33+00:00 c5d90e4b5cf8842746f359e45047f569b9325adb Merge more Select pseudo instructions in emitSelect() by allowing other instructions between them as long as they do not clobber CC. Debug value instructions are now moved down to below the new PHIs instead of erasing them. Review: Ulrich Weigand https://reviews.llvm.org/D67619 llvm-svn: 372873 
Merge more Select pseudo instructions in emitSelect() by allowing other
instructions between them as long as they do not clobber CC.

Debug value instructions are now moved down to below the new PHIs instead of
erasing them.

Review: Ulrich Weigand
https://reviews.llvm.org/D67619

llvm-svn: 372873
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11T11:16:48+00:00 Guillaume Chatelet gchatelet@google.com 2019-09-11T11:16:48+00:00 48904e9452de81375bd55d830d08e51cc8f2ec7e Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608 
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
Rename ExpandISelPseudo->FinalizeISel, delay register reservation 2019-06-19T00:25:39+00:00 Matt Arsenault Matthew.Arsenault@amd.com 2019-06-19T00:25:39+00:00 9cac4e6d1403554b06ec2fc9d834087b1234b695 This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757 
This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.

Patch by Matthias Braun

llvm-svn: 363757
Describe stack-id as an enum 2019-06-17T09:13:29+00:00 Sander de Smalen sander.desmalen@arm.com 2019-06-17T09:13:29+00:00 5d6ee76c16341cf0d7cb577d2316c71b31da7eb9 This patch changes MIR stack-id from an integer to an enum, and adds printing/parsing support for this in MIR files. The default stack-id '0' is now renamed to 'default'. This should make MIR tests that have stack objects with different stack-ids more descriptive. It also clarifies code operating on StackID. Reviewers: arsenm, thegameg, qcolombet Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D60137 llvm-svn: 363533 
This patch changes MIR stack-id from an integer to an enum,
and adds printing/parsing support for this in MIR files. The default
stack-id '0' is now renamed to 'default'.

This should make MIR tests that have stack objects with different stack-ids
more descriptive. It also clarifies code operating on StackID.

Reviewers: arsenm, thegameg, qcolombet

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D60137

llvm-svn: 363533
[SystemZ] Model floating-point control register 2019-05-13T09:47:26+00:00 Ulrich Weigand ulrich.weigand@de.ibm.com 2019-05-13T09:47:26+00:00 8e42f6ddc80f56e36264b1ec0f2d88df8486331e This adds the FPC (floating-point control register) as a reserved physical register and models its use by SystemZ instructions. Note that only the current rounding modes and the IEEE exception masks are modeled. *Changes* of the FPC due to exceptions (in particular the IEEE exception flags and the DXC) are not modeled. At this point, this patch is mostly NFC, but it will prevent scheduling of floating-point instructions across SPFC/LFPC etc. llvm-svn: 360570 
This adds the FPC (floating-point control register) as a reserved
physical register and models its use by SystemZ instructions.

Note that only the current rounding modes and the IEEE exception
masks are modeled.  *Changes* of the FPC due to exceptions (in
particular the IEEE exception flags and the DXC) are not modeled.

At this point, this patch is mostly NFC, but it will prevent
scheduling of floating-point instructions across SPFC/LFPC etc.

llvm-svn: 360570
[SystemZ] Remember to reset the NoPHIs property on MF in createPHIsForSelects() 2019-01-24T07:54:41+00:00 Jonas Paulsson paulsson@linux.vnet.ibm.com 2019-01-24T07:54:41+00:00 5916dea3383bd596be7c653063df0d4dc67fab49 After creating new PHI instructions during isel pseudo expansion, the NoPHIs property of MF should be reset in case it was previously set. Review: Ulrich Weigand llvm-svn: 352030 
After creating new PHI instructions during isel pseudo expansion, the NoPHIs
property of MF should be reset in case it was previously set.

Review: Ulrich Weigand
llvm-svn: 352030
[SystemZ] Fix test case for buildbot. 2019-01-23T10:29:12+00:00 Jonas Paulsson paulsson@linux.vnet.ibm.com 2019-01-23T10:29:12+00:00 6046d087c5b91d997ee025f38d83405bf0668adb llvm-clang-x86_64-expensive-checks-win triggered this assert: "llvm.dbg.value intrinsic requires a !dbg attachment" Hopefully, adding reasonable !dbg operands solves this. llvm-svn: 351939 
llvm-clang-x86_64-expensive-checks-win triggered this assert:

"llvm.dbg.value intrinsic requires a !dbg attachment"

Hopefully, adding reasonable !dbg operands solves this.

llvm-svn: 351939
[SystemZ] Handle DBG_VALUE instructions in two places in backend. 2019-01-23T07:42:26+00:00 Jonas Paulsson paulsson@linux.vnet.ibm.com 2019-01-23T07:42:26+00:00 961c47ec9833ae15ad4cbf71ecfb1403baed465c Two backend optimizations failed to handle cases when compiled with -g, due to failing to consider DBG_VALUE instructions. This was in SystemZTargetLowering::emitSelect() and SystemZElimCompare::getRegReferences(). This patch makes sure that DBG_VALUEs are recognized so that they do not affect these optimizations. Tests for branch-on-count, load-and-trap and consecutive selects. Review: Ulrich Weigand https://reviews.llvm.org/D57048 llvm-svn: 351928 
Two backend optimizations failed to handle cases when compiled with -g, due
to failing to consider DBG_VALUE instructions. This was in
SystemZTargetLowering::emitSelect() and
SystemZElimCompare::getRegReferences().

This patch makes sure that DBG_VALUEs are recognized so that they do not
affect these optimizations.

Tests for branch-on-count, load-and-trap and consecutive selects.

Review: Ulrich Weigand
https://reviews.llvm.org/D57048

llvm-svn: 351928