llvm-project.git/llvm/test/CodeGen/RISCV/float-mem.ll, branch users/mingmingl-llvm/samplefdo-profile-format

[RISCV] Prevent folding ADD_LO into load/store if we can't fold all uses. (#155935)

2025-09-09T16:25:36+00:00

If we don't fold all uses, we end up with an LUI that is used by an ADDI
and some loads/stores. This requires the LUI to write a different
register than the ADDI or the load/stores uses have to be scheduled
between the LUI and ADDI. It prevents macrofusion of the LUI+ADDI on
CPUs that support it. It prevents the use of PseudoMovAddr which
prevents the LUI+ADDI from being rematerializable.

This is based on a patch we have had in our downstream for a while that
we originally wrote because of macrofusion and rematerialization. I no
longer have any relevant performance or code size numbers for it.

---------

Co-authored-by: Jesse Huang 
Co-authored-by: Luke Lau

[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)

2024-01-07T20:09:44+00:00

R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).

GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).

Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1@plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.

[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

2023-09-19T17:02:19+00:00

When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVDeadRegisterDefinitions`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158759

[RISCV][CodeGen] Support Zfinx codegen

2023-05-02T16:13:38+00:00

This patch was split from D122918 . Co-Author: @liaolucy @realqhc

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D148874

[RISCV] Move compressible registers to the beginning of the FP allocation order.

2023-03-28T00:29:28+00:00

We don't have very many compressible FP instructions, just load and store.
These instruction require the FP register to be f8-f15.

This patch changes the FP allocation order to prioritize f10-f15 first.
These are also the FP argument registers. So I allocated them in reverse
order starting at f15 to avoid taking the first argument registers.
This appears to match gcc allocation order.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146488

[RISCV] Convert some tests to opaque pointers (NFC)

2022-12-19T12:01:08+00:00

[RISCV] Use check-prefixes to reduce check lines

2022-06-06T07:59:15+00:00

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D125083

[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.

2022-05-27T18:05:18+00:00

When lowering GlobalAddressNodes, we were removing a non-zero offset and
creating a separate ADD.

It already comes out of SelectionDAGBuilder with a separate ADD. The
ADD was being removed by DAGCombiner.

This patch disables the DAG combine so we don't have to reverse it.
Test changes all look to be instruction order changes. Probably due
to different DAG node ordering.

Differential Revision: https://reviews.llvm.org/D126558

[RISCV] Update some tests to use floating point ABI where it makes sense.

2022-02-24T17:27:57+00:00

Trying to reduce the diffs from D118333 for cases where it makes
more sense to use an FP ABI.

Reviewed By: asb, kito-cheng

Differential Revision: https://reviews.llvm.org/D120447

[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.

2021-07-20T16:22:06+00:00

If we need to shift left anyway we might be able to take advantage
of LUI implicitly shifting its immediate left by 12 to cover part
of the shift. This allows us to use more bits of the LUI immediate
to avoid an ADDI.

isDesirableToCommuteWithShift now considers compressed instruction
opportunities when deciding if commuting should be allowed.

I believe this is the same or similar to one of the optimizations
from D79492.

Reviewed By: luismarques, arcbbb

Differential Revision: https://reviews.llvm.org/D105417