llvm-project.git/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll, branch users/nico/python-2

[PowerPC] Add phony subregisters to cover the high half of the VSX registers. (#94628)

2024-07-29T15:17:04+00:00

On PowerPC there are 128 bit VSX registers. These registers are half
overlapped with 64 bit floating point registers (FPR). The 64 bit half
of the VXS register that does not overlap with the FPR does not overlap
with any other register class. The FPR are the only subregisters of the
VSX registers but they do not fully cover the 128 bit super register.
This leads to incorrect lane masks being created.

This patch adds phony registers for the other half of the VSX registers
in order to fully cover them and to make sure that the lane masks are
not the same for the VSX and the floating point register.

[PowerPC] Implement SchedModel for Power7

2023-09-13T06:55:07+00:00

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D158704

[PowerPC] Define SchedModel for Power8

2023-09-08T07:43:21+00:00

PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to
provide scheduling information. This patch re-writes the tablegen file
to define the scheduling information in the new SchedModel way, which
can bring improvements to some benchmarks.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D154488

[CodeGen] Using ZExt for extractelement indices.

2022-10-15T22:45:35+00:00

In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978

[PowerPC] Pre-commit unit test change for D132978

2022-10-12T18:26:57+00:00

[NFC] Clean-up typos in PowerPC CodeGen tests

2021-11-11T07:42:08+00:00

[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.

2017-12-22T17:18:13+00:00

This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.

I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.

llvm-svn: 321370

[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.

2017-12-18T19:21:56+00:00

This has the same issue as the early pass disabled in r321010.

llvm-svn: 321013

[PowerPC] Convert r+r instructions to r+i (pre and post RA)

2017-12-15T07:27:53+00:00

This patch adds the necessary infrastructure to convert instructions that
take two register operands to those that take a register and immediate if
the necessary operand is produced by a load-immediate. Furthermore, it uses
this infrastructure to perform such conversions twice - first at MachineSSA
and then pre-emit.

There are a number of reasons we may end up with opportunities for this
transformation, including but not limited to:
- X-Form instructions chosen since the exact offset isn't available at ISEL time
- Atomic instructions with constant operands (we will add patterns for this
  in the future)
- Tail duplication may duplicate code where one block contains this redundancy
- When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant
  comparands specially

Furthermore, this patch moves the initialization of PPCMIPeepholePass so that
it can be used for MIR tests.

llvm-svn: 320791

DAG: Avoid OOB when legalizing vector indexing

2017-01-10T22:02:30+00:00

If a vector index is out of bounds, the result is supposed to be
undefined but is not undefined behavior. Change the legalization
for indexing the vector on the stack so that an out of bounds
index does not create an out of bounds memory access.

llvm-svn: 291604