llvm-project.git/llvm/test/CodeGen/PowerPC/toc-data.ll, branch users/nico/python-2

[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)

2024-11-04T14:40:54+00:00

Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same interfaces for LLC.
This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU
to ppc64.

[PowerPC] Adjust operand order of ADDItoc to be consistent with other ADDI* nodes (#93642)

2024-06-06T09:15:53+00:00

Simultaneously, the `ADDItoc` machineinstr is generated in
`PPCISelDAGToDAG::Select` so the pattern is not used and can be removed.

[PowerPC] handle toc-data in load selection of fast-isel (#91916)

2024-05-24T03:09:37+00:00

Support the address selection for toc-data globals in fast isel. This
benefits instruction selection for fast-isel for toc data symbol for
example for load selection. This also aligns the code generation
with/without -mtocdata.

[PowerPC][AIX] 64-bit large code-model support for toc-data (#90619)

2024-05-21T18:00:24+00:00

This patch adds support for toc-data for 64-bit large code-model on AIX.
The sequence ADDIStocHA8/ADDItocL8 is used to access the data directly
from the TOC.
When emitting the instruction ADDIStocHA8, we check if the symbol has
toc-data attribute before creating a toc entry for it. When emitting the
instruction ADDItocL8, we use the LA8 instruction to load the address.

[PowerPC] 32-bit large code-model support for toc-data (#85129)

2024-04-17T13:24:53+00:00

This patch adds the pseudo op ADDItocL for 32-bit large code-model
support for toc-data.

Revert "[XCOFF][AIX] Peephole optimization for toc-data."

2023-08-15T14:40:35+00:00

This reverts commit 5e28d30f1fb10faf2db2f8bf0502e7fd72e6ac2e.

[XCOFF][AIX] Peephole optimization for toc-data.

2023-07-14T00:40:09+00:00

Followup to D101178 - peephole optimization that converts a
load address instruction and a consuming load/store into just the
load/store when its safe to do so.

eg: converts the 2 instruction code sequence
  la 4, i[TD](2)
  stw 3, 0(4)
to
  stw 3, i[TD](2)

Differential Revision: https://reviews.llvm.org/D101470

[PPC] Opaque pointer migration, part 2.

2022-10-11T17:24:06+00:00

The LIT test cases were migrated with the script provided by
Nikita Popov. Due to the size of the change it is split into
several parts.

Reviewed By: nemanja, nikic

Differential Revision: https://reviews.llvm.org/D135474

[PowerPC][AIX] Fallback to DAG-ISEL if global has toc-data attribute.

2022-01-17T21:21:38+00:00

FAST-ISEL should fall back to DAG-ISEL when a global variable has the
toc-data attribute. A number of the checks were duplicated in the lit
test becuase of
1) Slightly different output between -O0 and -O2 due to FAST-ISEL vs
   DAG-ISEL codegen.
2) In preperation of a peephole optimization that will run when
   optimizations are enabled.

Differential Revision: https://reviews.llvm.org/D115373

[PowerPC][AIX] Add toc-data support for 64-bit AIX small code model.

2021-12-01T15:56:21+00:00

The patch expands the existing 32-bit toc-data attribute support to 64-bit.
In both 32-bit and 64-bit it is supported for small code model only.

Differential Revision: https://reviews.llvm.org/D114654