llvm-project.git/llvm/test/CodeGen/PowerPC/optimize-vector.ll, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [PowerPC] catch v2i64 shift left by 1 is add case (#138772) 2025-05-13T15:26:46+00:00 RolandF77 55763885+RolandF77@users.noreply.github.com 2025-05-13T15:26:46+00:00 99f03096697625d14a536c5ac764ca530daa4008 Catch missing case in PPC BE for v2i64 x << 1 and generate x + x. 
Catch missing case in PPC BE for v2i64 x << 1 and generate x + x.
 [PowerPC] Improve code gen for vector add 2023-07-13T19:21:49+00:00 Nemanja Ivanovic nemanja.i.ibm@gmail.com 2023-07-04T14:48:12+00:00 329b8cd3e3826822f000175ed3e3dc6084e47e57 Improve codegen for vectors modulo additions. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D154447 
Improve codegen for vectors modulo additions.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D154447
[PowerPC] add testcase for vector add and shift 2023-07-04T14:45:19+00:00 Lei Huang lei@ca.ibm.com 2023-07-04T14:36:32+00:00 c7c3d71414ac250f377c067efd4848c353cec4cc