llvm-project.git/llvm/test/CodeGen/PowerPC/ctr-minmaxnum.ll, branch users/nico/python-2

[PPC] Opaque pointer migration, part 1.

2022-10-11T17:24:06+00:00

The LIT test cases were migrated with the script provided by
Nikita Popov. Due to the size of the change it is split into
several parts.

Reviewed By: nemanja, amyk, nikic, PowerPC

Differential Revision: https://reviews.llvm.org/D135470

Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

2020-07-28T14:00:11+00:00

This reverts commit bf544fa1c3cb80f24d85e84559fb11193846259f.

Fixed the typo in PPCInstrInfo.cpp.

Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

2020-07-27T21:07:00+00:00

This reverts commit adffce71538e219aab4eeb024819baa7687262ff.

This is breaking test-suite, revert while investigation.

[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support

2020-07-27T19:24:39+00:00

Per RFC http://lists.llvm.org/pipermail/llvm-dev/2020-April/141295.html
no one is making use of QPX/A2Q/BGQ/BGP CNK anymore.

This patch remove the support of QPX/A2Q in llvm, BGQ/BGP in clang,
CNK support in openmp/polly.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D83915

[PowerPC] Emit scalar fp min/max instructions

2019-10-29T00:13:33+00:00

VSX provides floating point minimum and maximum instructions that conform
to IEEE semantics. This legalizes the respective nodes and emits VSX code
for them. Furthermore, on Power9 cores we have xsmaxcdp and xsmincdp
instructions that conform to language semantics for the conditional operator
even in the presence of NaNs.

Differential revision: https://reviews.llvm.org/D62993

[PowerPC] Exploit the vector min/max instructions

2019-06-06T23:49:01+00:00

Use the PPC vector min/max instructions for computing the corresponding
operation as these should be faster than the compare/select sequences
we currently emit.

Differential revision: https://reviews.llvm.org/D47332

llvm-svn: 362759

[PowerPC] Add profitablilty check for conversion to mtctr loops

2017-10-12T16:43:33+00:00

Add profitability checks for modifying counted loops to use the mtctr instruction.

The latency of mtctr is only justified if there are more than 4 comparisons that
will be removed as a result.  Usually counted loops are formed relatively early
and before unrolling, so most low trip count loops often don't survive.  However
we want to ensure that if they do, we do not mistakenly update them to mtctr loops.

Use CodeMetrics to ensure we are only doing this for small loops with small trip counts.

Differential Revision: https://reviews.llvm.org/D38212

llvm-svn: 315592

Adding -verify-machineinstrs option to PowerPC tests

2016-08-03T18:17:35+00:00

Currently we have a number of tests that fail with -verify-machineinstrs.
To detect this cases earlier we add the option to the testcases with the
exception of tests that will currently fail with this option. PR 27456 keeps
track of this failures.

No code review, as discussed with Hal Finkel.

llvm-svn: 277624

[PowerPC] Map max/minnum intrinsics and fmax/fmin to ISD nodes for CTR-based loop legality

2016-03-27T05:40:56+00:00

Intrinsic::maxnum and Intrinsic::minnum, along with the associated libc
function calls (fmax[f], etc.) generally map to function calls after lowering.
For some vector types with QPX at least, however, we can legally lower these,
and we don't need to prohibit CTR-based loops on their account.

It turned out, however, that the logic that checked the opcodes associated with
intrinsics was broken (it would set the Opcode variable, but that variable was
later checked only if set for some otherwise-external function call.

This fixes the latter problem and adds the FMAX/MINNUM mappings.

llvm-svn: 264532

[PowerPC] Disable the CTR optimization in the presence of {min,max}num

2016-03-26T09:42:31+00:00

The minnum and maxnum intrinsics get lowered to libcalls which
invalidates the CTR optimization.

This fixes PR27083.

llvm-svn: 264508