llvm-project.git/llvm/test/CodeGen/PowerPC/crbits.ll, branch users/nico/python-2

[PowerPC] Retire PPCExpandISel pass (#84289)

2024-08-27T01:43:52+00:00

We can decide whether to expand isel or not in instruction selection
pass and early-if-conversion pass. The transformation implemented in
PPCExpandISel can be retired considering PPC backend doesn't generate
`isel` instructions post-RA.
Also if we are seeking performant branch-or-isel decision, we can turn
to selectoptimize pass.

---------

Co-authored-by: Kai Luo

[PowerPC] Implement SchedModel for Power7

2023-09-13T06:55:07+00:00

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D158704

[PowerPC] Enable track-subreg-liveness by default

2022-12-28T06:09:29+00:00

This option helps some MMA related cases to reduce unnecessary copies.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D108902

[PPC] Opaque pointer migration, part 1.

2022-10-11T17:24:06+00:00

The LIT test cases were migrated with the script provided by
Nikita Popov. Due to the size of the change it is split into
several parts.

Reviewed By: nemanja, amyk, nikic, PowerPC

Differential Revision: https://reviews.llvm.org/D135470

[DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

2022-09-27T12:54:52+00:00

This seems to be beneficial overall, except for midpoint-int.ll .

The X86 backend seems to generate zeroing that are not necesary.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D131260

[PowerPC] Autogenerate crbits.ll . NFC

2022-08-23T13:50:25+00:00

[PowerPC] Implement Set Boolean Condition Instructions

2020-10-26T23:42:51+00:00

This patch implements the set boolean condition instructions introduced in
POWER10.

The set boolean condition instructions (set[n]bc[r]) are used during
the following situations:
- sign/zero/any extending i1 to an i32 or i64,
- reg+reg, reg+imm or floating point comparisons being sign/zero extended to i32 or i64,
- spilling CR bits (using the setnbc instruction)

Differential Revision: https://reviews.llvm.org/D87705

[PowerPC] Add some InstAlias definitions

2020-05-24T14:05:28+00:00

Summary:
This patch add the InstAlias definitions for below instructions.

ADDI ADDIS ADDI8 ADDIS8
RLWINM8
ISEL ISEL8
OR OR_rec ORI ORI8 XORI8
CNTLZW8 CNTLZW8_rec
TEND TSR
RFEBB
NOR NOR_rec
MTCRF
SUBF SUBF_rec SUBFC SUBFC_rec
RLDICL_32_64
TW

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77559

[PowerPC] Ignore implicit register operands for MCInst

2020-04-16T16:22:43+00:00

Summary:
When doing the conversion: MachineInst -> MCInst, we should ignore the
implicit operands, it will expose more opportunity for InstiAlias.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77118

[PowerPC] Recommit r314244 with refactoring and off by default

2017-11-30T13:39:10+00:00

This re-commits everything that was pulled in r314244. The transformation
is off by default (patch to enable it to follow). The code is refactored
to have a single entry-point and provide fine-grained control over patterns
that it selects. This patch also fixes the bugs in the original code.

Everything that failed with the original patch has been re-tested with this
patch (with the transformation turned on). So the patch to turn this on is
soon to follow.

Differential Revision: https://reviews.llvm.org/D38575

llvm-svn: 319434