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<title>llvm-project.git/llvm/test/CodeGen/PowerPC/const-splat-array-init.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[PowerPC] Add `SDNPMemOperand` to some nodes (#115580)</title>
<updated>2024-11-15T17:36:56+00:00</updated>
<author>
<name>Sergei Barannikov</name>
<email>barannikov88@gmail.com</email>
</author>
<published>2024-11-15T17:36:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=032014ef103157bfd8403418538e25f3f58efa9d'/>
<id>032014ef103157bfd8403418538e25f3f58efa9d</id>
<content type='text'>
Nodes created with `getMemIntrinsicNode` have memory operands. In order
for operands to be propagated to machine instructions, the nodes should
have `SDNPMemOperand` property.

Similar to 3c8c385a.
</content>
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<pre>
Nodes created with `getMemIntrinsicNode` have memory operands. In order
for operands to be propagated to machine instructions, the nodes should
have `SDNPMemOperand` property.

Similar to 3c8c385a.
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC] Define SchedModel for Power8</title>
<updated>2023-09-08T07:43:21+00:00</updated>
<author>
<name>Qiu Chaofan</name>
<email>qiucofan@cn.ibm.com</email>
</author>
<published>2023-09-08T07:41:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b922a3621116b404d868af8b74cab25ab78555be'/>
<id>b922a3621116b404d868af8b74cab25ab78555be</id>
<content type='text'>
PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to
provide scheduling information. This patch re-writes the tablegen file
to define the scheduling information in the new SchedModel way, which
can bring improvements to some benchmarks.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D154488
</content>
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<pre>
PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to
provide scheduling information. This patch re-writes the tablegen file
to define the scheduling information in the new SchedModel way, which
can bring improvements to some benchmarks.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D154488
</pre>
</div>
</content>
</entry>
<entry>
<title>[PowerPC][NFC] add const-splat-array-init.ll</title>
<updated>2023-02-22T01:24:12+00:00</updated>
<author>
<name>Ting Wang</name>
<email>Ting.Wang.SH@ibm.com</email>
</author>
<published>2023-02-22T01:24:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=00ed95c3a2223364a32941ecf725cf36298bd514'/>
<id>00ed95c3a2223364a32941ecf725cf36298bd514</id>
<content type='text'>
Add test case and will show combiner can improve these.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D144235
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<pre>
Add test case and will show combiner can improve these.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D144235
</pre>
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</content>
</entry>
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