This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.

This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.

This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.

Enables the terminal rule for remaining targets

Reland #154439.  Reverted with #155914.

Account for:
- Windows `ptxas` outputting error messages to `stdout` instead of
`stderr`
- Tests in `llvm/test/DebugInfo/NVPTX`

Reverts llvm/llvm-project#154439 in order to resolve
https://github.com/llvm/llvm-project/pull/154439#issuecomment-3234638253.

ToT `lit` currently assumes that a given `ptxas` version supports all
capabilities of prior `ptxas` releases. This approach was flexible
enough to support the removal of 32-bit address compilation from `ptxas`
in CUDA 12.1, but it struggles with the removal of Volta and prior
compilation in CUDA 13.0.

To deal with this, this PR refactors how `lit` defines the set of
features available for a given `ptxas` version. It invokes `ptxas` not
just to get its version, but also to get the list of supported SMs,
supported PTX ISA versions, and support for 32-bit compilation.

This approach should be flexible enough to deal with the changing
support matrix of `ptxas` as it goes forward. One obvious downside is
that this relies on parsing the `stdout` of `ptxas`, something that's
inherently unstable. But, IMO, this is something that we can fix as
needed.

When assigning numbers to registers, skip any with neither uses nor
defs. This is will not have any impact at all on the final SASS but it
makes for slightly more readable PTX. This change should also ensure
that future minor changes are less likely to cause noisy diffs in
register numbering.

This MR adds support for cmpxchg instructions with syncscope.

- Adds a new definition for atomic 3-operand instructions, with constant
operands for sem, scope and addsp.
- Lowers cmpxchg SDNodes populating sem, scope and addsp using
SDNodeXForms.
- Handle syncscope correctly for emulation loops in AtomicExpand, in
bracketInstructionWithFences.
- Modifies emitLeadingFence, emitTrailingFence to accept SyncScope as a
parameter. Modifies implementation of these in other backends, with the
parameter being ignored.
- Tests for a _slice_ of all possible combinations of the cmpxchg
instruction (with modifications to cmpxchg.py)

---------

Co-authored-by: gonzalobg <65027571+gonzalobg@users.noreply.github.com>

This change cleans up DAG-to-DAG instruction selection around FTZ and
SETP comparison mode. Largely these changes do not impact functionality
though support for `{sin.cos}.approx.ftz.f32` is added.

In most cases, the type information attached to load and store
instructions is meaningless and inconsistently applied. We can usually
use ".b" loads and avoid the complexity of trying to assign the correct
type. The one expectation is sign-extending load, which will continue to
use ".s" to ensure the sign extension into a larger register is done
correctly.