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<title>llvm-project.git/llvm/test/CodeGen/MSP430/selectcc.ll, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"</title>
<updated>2023-10-09T11:31:32+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-10-09T11:31:32+00:00</published>
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<id>7b3bbd83c0c24087072ec5b22a76799ab31f87d5</id>
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This reverts commit 2501ae58e3bb9a70d279a56d7b3a0ed70a8a852c.

Reverted due to various buildbot failures.
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This reverts commit 2501ae58e3bb9a70d279a56d7b3a0ed70a8a852c.

Reverted due to various buildbot failures.
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<entry>
<title>[CodeGen] Really renumber slot indexes before register allocation (#67038)</title>
<updated>2023-10-09T10:44:41+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2023-10-09T10:44:41+00:00</published>
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<id>2501ae58e3bb9a70d279a56d7b3a0ed70a8a852c</id>
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PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries for instructions which
had been erased. Fix this to make the register allocator's live range
length heuristics even less dependent on the history of how instructions
have been added to and removed from SlotIndexes's maps.</content>
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PR #66334 tried to renumber slot indexes before register allocation, but
the numbering was still affected by list entries for instructions which
had been erased. Fix this to make the register allocator's live range
length heuristics even less dependent on the history of how instructions
have been added to and removed from SlotIndexes's maps.</pre>
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</entry>
<entry>
<title>[DAGCombiner] add operation legality checks before creating shift ops (PR43542)</title>
<updated>2019-10-03T21:34:04+00:00</updated>
<author>
<name>Sanjay Patel</name>
<email>spatel@rotateright.com</email>
</author>
<published>2019-10-03T21:34:04+00:00</published>
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<id>288079aafdbde5d408db86a697ee5b19a0902f1d</id>
<content type='text'>
As discussed on llvm-dev and:
https://bugs.llvm.org/show_bug.cgi?id=43542
...we have transforms that assume shift operations are legal and transforms to
use them are profitable, but that may not hold for simple targets.

In this case, the MSP430 target custom lowers shifts by repeating (many)
simpler/fixed ops. That can be avoided by keeping this code as setcc/select.

Differential Revision: https://reviews.llvm.org/D68397

llvm-svn: 373666
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As discussed on llvm-dev and:
https://bugs.llvm.org/show_bug.cgi?id=43542
...we have transforms that assume shift operations are legal and transforms to
use them are profitable, but that may not hold for simple targets.

In this case, the MSP430 target custom lowers shifts by repeating (many)
simpler/fixed ops. That can be avoided by keeping this code as setcc/select.

Differential Revision: https://reviews.llvm.org/D68397

llvm-svn: 373666
</pre>
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</entry>
<entry>
<title>[MSP430] add tests for unwanted shift codegen; NFC (PR43542)</title>
<updated>2019-10-03T14:54:03+00:00</updated>
<author>
<name>Sanjay Patel</name>
<email>spatel@rotateright.com</email>
</author>
<published>2019-10-03T14:54:03+00:00</published>
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<id>38c265fe261586653ee3bb9cbf1f862afe2b1457</id>
<content type='text'>
llvm-svn: 373607
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llvm-svn: 373607
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