llvm-project.git/llvm/test/CodeGen/MIR, branch users/nico/python-2

[NVPTX] Fixup v2i8 parameter and return lowering (#145585)

2025-06-27T16:26:10+00:00

This change fixes v2i8 lowering for parameters and returned values. As
part of this work, I move the lowering for return values to use generic
ISD::STORE nodes as these are more flexible and have existing
legalization handling.

Note that calling a function with v2i8 arguments or returns is still not
working but this is left for a subsequent change as this MR is already
fairly large.

Partially addresses #128853

[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)

2025-06-24T09:09:36+00:00

Use a function attribute (amdgpu-dynamic-vgpr) instead of a subtarget
feature, as requested in #130030.

[NVPTX] Rename register classes after float register removal (NFC) (#145255)

2025-06-23T17:53:36+00:00

[MIRParser] Report register class errors in a deterministic order (#142928)

2025-06-06T09:03:34+00:00

[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#141711)

2025-05-29T19:24:31+00:00

[NVPTX] Remove Float register classes (#140487)

2025-05-21T18:33:57+00:00

These classes are redundant, as the untyped "Int" classes can be used
for all float operations. This change is intended to be as minimal as
possible and leaves the many potential simplifications and refactors
this exposes as future work.

[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#139292)

2025-05-13T20:36:09+00:00

PTX 8.8+ introduces 256-bit-wide vector loads/stores under certain
conditions. This change extends the backend to lower these loads/stores.
It also overrides getLoadStoreVecRegBitWidth for NVPTX, allowing the
LoadStoreVectorizer to create these wider vector operations.

See the spec for the three relevant PTX instructions here:
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-ld-global-nc
- https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-st

[CodeGen] Parse nusw flag (#138856)

2025-05-08T08:40:15+00:00

Fixes #127781

[AArch64] Correct position of CFI Instruction for Pointer Authentication (#137795)

2025-05-06T09:31:04+00:00

This reverts partially this commit
0b73b5af60f2c544892b9dd68b4fa43eeff52fc1.
This is not a clear revert because other changes already landed.
CFI directives like `.cfi_negate_ra_state` must be emitted after the
instruction.
If the execution is stopped before the `paciasp` instruction is executed
the debugger/unwinder would try to authenticated the return address as
the `.cfi_negate_ra_state` already indicates it got signed.

fixes: #137802

[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)

2025-04-15T22:17:33+00:00

Previously the AnnotateKernelFeatures pass infers two attributes:
amdgpu-calls and amdgpu-stack-objects, which are used to help determine
if flat scratch init is allowed. PR #118907 created the
amdgpu-no-flat-scratch-init attribute. Continuing with that work, this
patch makes use of this attribute to determine flat scratch init,
replacing amdgpu-calls and amdgpu-stack-objects. This also leads to the
removal of the AnnotateKernelFeatures pass.