llvm-project.git/llvm/test/CodeGen/M68k, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. Rename ExpandLargeFpConvertPass to ExpandFpPass (#131128) 2025-03-14T12:11:45+00:00 Frederik Harwath frederik.harwath@amd.com 2025-03-14T12:11:45+00:00 6962cf1700c28d76882e188d8e401486fe051bd4 This is meant as a preparation for PR #130988 "[AMDGPU] Implement IR expansion for frem instruction" which implements the expansion of another instruction in this pass. The more general name seems more appropriate given this change and quite reasonable even without it. 
This is meant as a preparation for PR #130988 "[AMDGPU] Implement IR
expansion for frem instruction" which implements the expansion of
another instruction in this pass. The more general name seems more
appropriate given this change and quite reasonable even without it.
 [M68k] always use movem for register spills (#106715) 2025-02-01T01:42:40+00:00 Janis Heims technoelf@undertheprinter.com 2025-02-01T01:42:40+00:00 1eac7cd5d1a3738f43d737d74ea299e08a1c3b61 Fixes #106206 and #106209. 
Fixes #106206 and #106209.
 [M68k] Fix llc pass test after 3630d9ef65b30af7e4ca78e668649bbc48b5be66 2025-01-23T13:28:25+00:00 Michael Liao michael.hliao@gmail.com 2025-01-23T13:27:09+00:00 590e5e20b12f9fd956d0ba7de83aa2ab44c9faeb 






[M68k,MSP430,test] Change llc -march= to -mtriple=
2024-12-15T18:09:30+00:00

Fangrui Song
i@maskray.me

2024-12-15T18:09:30+00:00

171056ff5778c40df916c5a4cea84ea6320b965f

Similar to 806761a7629df268c8aed49657aeccffa6bca449





Similar to 806761a7629df268c8aed49657aeccffa6bca449







[M68k] Add remaining addressing modes for Atomic operations (#115523)
2024-12-12T17:11:23+00:00

knickish
knickish@gmail.com

2024-12-12T17:11:23+00:00

4cce10743d2275710d3d2e0de8013386a9799092

Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.

The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode




Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.

The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode






[M68k] Handle 16 bit MOVs to and from CCR  (#114714)
2024-11-27T17:37:57+00:00

knickish
knickish@gmail.com

2024-11-27T17:37:57+00:00

c29e895ad2bce8ca36debd8ef09d0540dabc99b6

Builds on @TechnoElf 's CCR MOV pr
https://github.com/llvm/llvm-project/pull/107591 and adds some tests.

Fixes https://github.com/llvm/llvm-project/issues/106210.

---------

Co-authored-by: TechnoElf <technoelf@undertheprinter.com>




Builds on @TechnoElf 's CCR MOV pr
https://github.com/llvm/llvm-project/pull/107591 and adds some tests.

Fixes https://github.com/llvm/llvm-project/issues/106210.

---------

Co-authored-by: TechnoElf <technoelf@undertheprinter.com>






[M68k] fix call frame destruction elimination when returning structs (#107579)
2024-11-10T23:43:25+00:00

Janis Heims
janis.heims@undertheprinter.com

2024-11-10T23:43:25+00:00

3006dddfe091bcb95924d72dddbb84f73186a344

Fixes #106213.

This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.




Fixes #106213.

This adjusts `eliminateCallFramePseudoInstr` to match the behaviour of
the X86 backend.






[M68k] implement large code model (#106381)
2024-11-08T05:46:52+00:00

Janis Heims
janis.heims@undertheprinter.com

2024-11-08T05:46:52+00:00

2f40e3e713efb550c05ff5f911ab4ce2e4a8dddf

Fixes #106208.




Fixes #106208.






Revert "TLS loads opimization (hoist)" (#114740)
2024-11-07T09:10:28+00:00

abhishek-kaushik22
abhishek.kaushik@intel.com

2024-11-07T09:10:28+00:00

d2aff182d379c9b84cebe0fdf58907f4de768f1e

This reverts commit c31014322c0b5ae596da129cbb844fb2198b4ef4.

Based on the discussions in #112772, this pass is not needed after the
introduction of `llvm.threadlocal.address` intrinsic.

Fixes https://github.com/llvm/llvm-project/issues/112771.




This reverts commit c31014322c0b5ae596da129cbb844fb2198b4ef4.

Based on the discussions in #112772, this pass is not needed after the
introduction of `llvm.threadlocal.address` intrinsic.

Fixes https://github.com/llvm/llvm-project/issues/112771.






[M68k] ARII atomic load/store (#108982)
2024-10-18T15:49:26+00:00

knickish
knickish@gmail.com

2024-10-18T15:49:26+00:00

e13f1d1daf9b76134c3585e8250941920bdf3da6

Only ARI was supported, this PR adds ARII support for atomic
loads/stores (also with zero displacement). Closes #107939




Only ARI was supported, this PR adds ARII support for atomic
loads/stores (also with zero displacement). Closes #107939