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<title>llvm-project.git/llvm/test/CodeGen/LoongArch, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Reland "[LoongArch] Add `isSafeToMove` hook to prevent unsafe instruction motion" (#167465)</title>
<updated>2025-11-12T00:51:08+00:00</updated>
<author>
<name>hev</name>
<email>wangrui@loongson.cn</email>
</author>
<published>2025-11-12T00:51:08+00:00</published>
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<id>ea10026b64f66b3b69c0545db20f9daa8579f5cb</id>
<content type='text'>
This patch introduces a new virtual method
`TargetInstrInfo::isSafeToMove()` to allow backends to control whether a
machine instruction can be safely moved by optimization passes.

The `BranchFolder` pass now respects this hook when hoisting common
code. By default, all instructions are considered safe to to move.

For LoongArch, `isSafeToMove()` is overridden to prevent
relocation-related instruction sequences (e.g. PC-relative addressing
and calls) from being broken by instruction motion. Correspondingly,
`isSchedulingBoundary()` is updated to reuse this logic for consistency.

Relands #163725</content>
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<pre>
This patch introduces a new virtual method
`TargetInstrInfo::isSafeToMove()` to allow backends to control whether a
machine instruction can be safely moved by optimization passes.

The `BranchFolder` pass now respects this hook when hoisting common
code. By default, all instructions are considered safe to to move.

For LoongArch, `isSafeToMove()` is overridden to prevent
relocation-related instruction sequences (e.g. PC-relative addressing
and calls) from being broken by instruction motion. Correspondingly,
`isSchedulingBoundary()` is updated to reuse this logic for consistency.

Relands #163725</pre>
</div>
</content>
</entry>
<entry>
<title>[LoongArch] Initial implementation for `enableMemCmpExpansion` hook (#166526)</title>
<updated>2025-11-10T03:43:37+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-11-10T03:43:37+00:00</published>
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<id>f734cebc396bfb0a3523d205071764f689432ab4</id>
<content type='text'>
After overriding `TargetTransformInfo::enableMemCmpExpansion` in this
commit, `MergeICmps` and `ExpandMemCmp` passes will be enabled on
LoongArch.</content>
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<pre>
After overriding `TargetTransformInfo::enableMemCmpExpansion` in this
commit, `MergeICmps` and `ExpandMemCmp` passes will be enabled on
LoongArch.</pre>
</div>
</content>
</entry>
<entry>
<title>[LoongArch][NFC] Pre-commit tests for memcmp expansion (#166718)</title>
<updated>2025-11-10T01:59:36+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-11-10T01:59:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5ba0c7c12674303574731cec3ba5d168b41cfac3'/>
<id>5ba0c7c12674303574731cec3ba5d168b41cfac3</id>
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Test cases are similar as riscv.</content>
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<pre>
Test cases are similar as riscv.</pre>
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</content>
</entry>
<entry>
<title>[LoongArch] Override hooks to enable sink-and-fold support in MachineSink (#163721)</title>
<updated>2025-11-06T06:02:55+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-11-06T06:02:55+00:00</published>
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<id>868f23f8cc1aec26c40f070d85f70ed3cb6b72cb</id>
<content type='text'>
Add option `loongarch-enable-sink-fold` to enable sink-fold and set
`true` as default. This pass can fold `addi+load/store` to a single
`load/store` with offset.</content>
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<pre>
Add option `loongarch-enable-sink-fold` to enable sink-fold and set
`true` as default. This pass can fold `addi+load/store` to a single
`load/store` with offset.</pre>
</div>
</content>
</entry>
<entry>
<title>[llvm][LoongArch] Introduce LASX and LSX conversion intrinsics (#157818)</title>
<updated>2025-11-05T12:36:38+00:00</updated>
<author>
<name>hev</name>
<email>wangrui@loongson.cn</email>
</author>
<published>2025-11-05T12:36:38+00:00</published>
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<id>a4105707eeaf53c13c2f09298d762995267c7717</id>
<content type='text'>
This patch introduces the LASX and LSX conversion intrinsics:

- &lt;8 x float&gt; @llvm.loongarch.lasx.cast.128.s(&lt;4 x float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.cast.128.d(&lt;2 x double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.cast.128(&lt;2 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.concat.128.s(&lt;4 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.concat.128.d(&lt;2 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.concat.128(&lt;2 x i64&gt;, &lt;2 x i64&gt;)
- &lt;4 x float&gt; @llvm.loongarch.lasx.extract.128.lo.s(&lt;8 x float&gt;)
- &lt;2 x double&gt; @llvm.loongarch.lasx.extract.128.lo.d(&lt;4 x double&gt;)
- &lt;2 x i64&gt; @llvm.loongarch.lasx.extract.128.lo(&lt;4 x i64&gt;)
- &lt;4 x float&gt; @llvm.loongarch.lasx.extract.128.hi.s(&lt;8 x float&gt;)
- &lt;2 x double&gt; @llvm.loongarch.lasx.extract.128.hi.d(&lt;4 x double&gt;)
- &lt;2 x i64&gt; @llvm.loongarch.lasx.extract.128.hi(&lt;4 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.insert.128.lo.s(&lt;8 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.insert.128.lo.d(&lt;4 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.insert.128.lo(&lt;4 x i64&gt;, &lt;2 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.insert.128.hi.s(&lt;8 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.insert.128.hi.d(&lt;4 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.insert.128.hi(&lt;4 x i64&gt;, &lt;2 x i64&gt;)</content>
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<pre>
This patch introduces the LASX and LSX conversion intrinsics:

- &lt;8 x float&gt; @llvm.loongarch.lasx.cast.128.s(&lt;4 x float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.cast.128.d(&lt;2 x double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.cast.128(&lt;2 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.concat.128.s(&lt;4 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.concat.128.d(&lt;2 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.concat.128(&lt;2 x i64&gt;, &lt;2 x i64&gt;)
- &lt;4 x float&gt; @llvm.loongarch.lasx.extract.128.lo.s(&lt;8 x float&gt;)
- &lt;2 x double&gt; @llvm.loongarch.lasx.extract.128.lo.d(&lt;4 x double&gt;)
- &lt;2 x i64&gt; @llvm.loongarch.lasx.extract.128.lo(&lt;4 x i64&gt;)
- &lt;4 x float&gt; @llvm.loongarch.lasx.extract.128.hi.s(&lt;8 x float&gt;)
- &lt;2 x double&gt; @llvm.loongarch.lasx.extract.128.hi.d(&lt;4 x double&gt;)
- &lt;2 x i64&gt; @llvm.loongarch.lasx.extract.128.hi(&lt;4 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.insert.128.lo.s(&lt;8 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.insert.128.lo.d(&lt;4 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.insert.128.lo(&lt;4 x i64&gt;, &lt;2 x i64&gt;)
- &lt;8 x float&gt; @llvm.loongarch.lasx.insert.128.hi.s(&lt;8 x float&gt;, &lt;4 x
float&gt;)
- &lt;4 x double&gt; @llvm.loongarch.lasx.insert.128.hi.d(&lt;4 x double&gt;, &lt;2 x
double&gt;)
- &lt;4 x i64&gt; @llvm.loongarch.lasx.insert.128.hi(&lt;4 x i64&gt;, &lt;2 x i64&gt;)</pre>
</div>
</content>
</entry>
<entry>
<title>[LoongArch] Make fminnum/fmaxnum legal for lsx/lasx (#162768)</title>
<updated>2025-11-03T02:14:33+00:00</updated>
<author>
<name>Zhaoxin Yang</name>
<email>yangzhaoxin@loongson.cn</email>
</author>
<published>2025-11-03T02:14:33+00:00</published>
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<id>32938ffc710b941c68c1b40b07bd456801d3434a</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[LoongArch][NFC] Pre-commit tests for `vclo` which counts the leading ones for each vector elements (#165980)</title>
<updated>2025-11-01T09:37:47+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-11-01T09:37:47+00:00</published>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[LoongArch][NFC] Pre-commit tests for sink-and-fold (#163928)</title>
<updated>2025-11-01T06:50:27+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-11-01T06:50:27+00:00</published>
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<id>8e14e2704e0c63e925211c68c061a56f6d281e41</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[LoongArch] Make ceil,floor,trunc,roundeven legal for lsx/lasx (#165217)</title>
<updated>2025-11-01T01:29:00+00:00</updated>
<author>
<name>Zhaoxin Yang</name>
<email>yangzhaoxin@loongson.cn</email>
</author>
<published>2025-11-01T01:29:00+00:00</published>
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<pre>
</pre>
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</entry>
<entry>
<title>[LoongArch][NFC] Pre-commit tests for vector type avg{floor/ceil}{s/u} (#165821)</title>
<updated>2025-10-31T06:13:30+00:00</updated>
<author>
<name>ZhaoQi</name>
<email>zhaoqi01@loongson.cn</email>
</author>
<published>2025-10-31T06:13:30+00:00</published>
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</pre>
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