llvm-project.git/llvm/test/CodeGen/AVR/shift.ll, branch users/nico/python-2 Unnamed repository; edit this file 'description' to name the repository. [AVR,test] Change llc -march= to -mtriple= 2024-12-15T18:26:33+00:00 Fangrui Song i@maskray.me 2024-12-15T18:26:33+00:00 9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3 Similar to 806761a7629df268c8aed49657aeccffa6bca449 -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead of rejecting it outrightly. 
Similar to 806761a7629df268c8aed49657aeccffa6bca449

-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.
[MachineLICM] Hoist copies of constant physical register (#93285) 2024-05-29T06:10:01+00:00 Pengcheng Wang wangpengcheng.pp@bytedance.com 2024-05-29T06:10:01+00:00 4e0bd3fab4b6a54342c9bed14f205895da3cf0d9 Previously, we just check if the source is a virtual register and this prevents some potential hoists. We can see some improvements in AArch64/RISCV tests. 
Previously, we just check if the source is a virtual register and
this prevents some potential hoists.

We can see some improvements in AArch64/RISCV tests.
 [AVR] Expand shifts of all types except int8 and int16 2023-07-19T03:57:00+00:00 Patryk Wychowaniec pwychowaniec@pm.me 2023-07-19T03:54:34+00:00 4e831753b9cf8745e9bf251f775f2399c9ef4138 Currently our AVRShiftExpand pass expands only 32-bit shifts, with the assumption that other kinds of shifts (e.g. 64-bit ones) are automatically reduced to 8-bit ones by LLVM during ISel. However this is not always true and causes problems in the rust-lang runtime. This commit changes the logic a bit, so that instead of expanding only 32-bit shifts, we expand shifts of all types except 8-bit and 16-bit. This is not the most optimal solution, because 64-bit shifts can be expanded to 32-bit shifts which has been deeply optimized. I've checked the generated code using rustc + simavr, and all shifts seem to behave correctly. Spotted in the wild in rustc: https://github.com/rust-lang/compiler-builtins/issues/523 https://github.com/rust-lang/rust/issues/112140 Reviewed By: benshi001 Differential Revision: https://reviews.llvm.org/D154785 
Currently our AVRShiftExpand pass expands only 32-bit shifts, with the
assumption that other kinds of shifts (e.g. 64-bit ones) are
automatically reduced to 8-bit ones by LLVM during ISel.

However this is not always true and causes problems in the rust-lang runtime.

This commit changes the logic a bit, so that instead of expanding only
32-bit shifts, we expand shifts of all types except 8-bit and 16-bit.

This is not the most optimal solution, because 64-bit shifts can be
expanded to 32-bit shifts which has been deeply optimized.

I've checked the generated code using rustc + simavr, and all shifts
seem to behave correctly.

Spotted in the wild in rustc:
https://github.com/rust-lang/compiler-builtins/issues/523
https://github.com/rust-lang/rust/issues/112140

Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D154785
[NFC][Codegen][AVR] Make shift.ll autogenerate-able 2022-12-24T16:26:42+00:00 Roman Lebedev lebedev.ri@gmail.com 2022-12-24T16:12:27+00:00 3bb5ddd1756d4573d3104f8b86d2973dbc550402 






[AVR] Optimize int16 airthmetic right shift for shift amount 7/14/15
2022-03-26T06:53:27+00:00

Ben Shi
ben.shi@streamcomputing.com

2022-03-26T03:24:18+00:00

bce2e208e08f62dd362566e43b16cbfece459bec

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115618





Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115618







[AVR] Optimize int16 shift operation for shift amount greater than 8
2022-01-04T11:48:50+00:00

Ben Shi
ben.shi@streamcomputing.com

2022-01-04T11:14:30+00:00

99e7bf46c9e34644a8c0033684798dcafc790200

Skip operation on the lower byte in int16 logical left shift when
shift amount is greater than 8.

Skip operation on the higher byte in int16 logical & arithmetic
right shift when shift amount is greater than 8.

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115594





Skip operation on the lower byte in int16 logical left shift when
shift amount is greater than 8.

Skip operation on the higher byte in int16 logical & arithmetic
right shift when shift amount is greater than 8.

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115594







[AVR] Optimize int8 arithmetic right shift 6 bits
2022-01-04T10:36:03+00:00

Ben Shi
ben.shi@streamcomputing.com

2022-01-04T03:20:29+00:00

f4ef79306cee2b5866aff681174f16b816810c4a

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115593





Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115593







Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"
2022-01-04T04:14:15+00:00

Ben Shi
ben.shi@streamcomputing.com

2022-01-04T04:14:15+00:00

9fb4e79d06aa690c611c0ef601c134f57788590a

This reverts commit 5723261370b45fa4d0d295845c6ef9e223f2ff4a.

There are failures as reported in

https://lab.llvm.org/buildbot#builders/16/builds/21638
https://lab.llvm.org/buildbot#builders/104/builds/5394





This reverts commit 5723261370b45fa4d0d295845c6ef9e223f2ff4a.

There are failures as reported in

https://lab.llvm.org/buildbot#builders/16/builds/21638
https://lab.llvm.org/buildbot#builders/104/builds/5394







[AVR] Optimize int8 arithmetic right shift 6 bits
2022-01-04T03:20:29+00:00

Ben Shi
ben.shi@streamcomputing.com

2022-01-04T03:20:29+00:00

5723261370b45fa4d0d295845c6ef9e223f2ff4a

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115593





Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D115593







[AVR] Fix a bug in 16-bit shifts
2021-02-14T03:54:55+00:00

Ben Shi
powerman1st@163.com

2021-02-14T03:54:55+00:00

efb1cb752bf12149af9c773f702a757ba9721649

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D96590





Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D96590