llvm-project.git/llvm/test/CodeGen/AVR/pseudo, branch users/nico/python-2

[AVR,test] Change llc -march= to -mtriple=

2024-12-15T18:26:33+00:00

Similar to 806761a7629df268c8aed49657aeccffa6bca449

-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.

Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.

[AVR] Fix incorrect expansion of pseudo instruction ROLBRd

2023-06-10T16:20:43+00:00

Since ROLBRd needs an implicit R1 (on AVR) or an implicit R17 (on AVRTiny),
we split ROLBRd to ROLBRdR1 (on AVR) and ROLBRdR17 (on AVRTiny).

Reviewed By: aykevl, Patryk27

Differential Revision: https://reviews.llvm.org/D152248

[AVR][NFC][test] Suppement a test of the pseudo instruction RORBRd

2023-06-04T15:19:21+00:00

Reviewed By: aykevl, Patryk27

Differential Revision: https://reviews.llvm.org/D152087

[AVR] Fix incorrect operands of pseudo instruction 'ROLBRd'

2023-06-04T03:08:57+00:00

Fixes https://github.com/llvm/llvm-project/issues/63098

Reviewed by: benshi001

Differential Revision: https://reviews.llvm.org/D152063

[AVR] Fix an issue of writing 16-bit ports

2023-04-17T07:35:33+00:00

For 16-bit ports, the normal devices reqiure writing high byte first
and then low byte. But the XMEGA devices require the reverse order.

Fixes https://github.com/llvm/llvm-project/issues/58395

Reviewed By: aykevl, jacquesguan

Differential Revision: https://reviews.llvm.org/D141752

[AVR] Fix incorrect expansion of pseudo instructions LPMWRdZ/ELPMWRdZ

2023-04-06T07:27:04+00:00

The 'ELPM' instruction has three forms:

--------------------------
| form        | feature  |
| ----------- | -------- |
| ELPM        | hasELPM  |
| ELPM Rd, Z  | hasELPMX |
| ELPM Rd, Z+ | hasELPMX |
--------------------------

The second form is always used in the expansion of pseudo instructions
LPMWRdZ/ELPMWRdZ. But for devices without ELPMX and with only ELPM,
only the first form can be used.

Reviewed By: aykevl, Miss_Grape

Differential Revision: https://reviews.llvm.org/D141264

[AVR] Do not emit 'LPM Rd, Z' on devices without FeatureLPMX

2023-03-24T09:47:24+00:00

The 'LPM' instruction has three forms:

------------------------
| form       | feature |
| ---------- | --------|
| LPM        | hasLPM  |
| LPM Rd, Z  | hasLPMX |
| LPM Rd, Z+ | hasLPMX |
------------------------

The second form is always selected in ISelDAGToDAG, even on devices
without FeatureLPMX. This patch emits "LPM + MOV" on devices with
only FeatureLPM.

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D141246

[AVR] Fix incorrect expansion of the pseudo 'ELPMBRdZ' instruction

2023-03-21T03:33:56+00:00

The 'ELPM' instruction has three forms:

--------------------------
| form        | feature  |
| ----------- | -------- |
| ELPM        | hasELPM  |
| ELPM Rd, Z  | hasELPMX |
| ELPM Rd, Z+ | hasELPMX |
--------------------------

The second form is always used in the expansion of the pseudo
instruction 'ELPMBRdZ'. But for devices without ELPMX but only
with ELPM, only the first form can be emitted.

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D141221

[AVR] Do not emit instructions invalid for attiny10

2022-12-22T16:04:53+00:00

The attiny4/attiny5/attiny9/attiny10 have a slightly modified
instruction set that drops a number of useful instructions. This patch
makes sure to not emit them on these "reduced tiny" cores.

The affected instructions are:

  * lds and sts (load/store directly from data)
  * ldd and std (load/store with displacement)
  * adiw and sbiw (add/sub register pairs)
  * various other instructions that were emitted without checking
    whether the chip actually supports them (movw, adiw, etc)

There is a variant on lds and sts on these chips, but it can only
address a limited portion of the address space and is mainly useful to
load/store I/O registers (as an extension to the in and out
instructions). I have not implemented it here, implementing it can be
done in a separate patch.

This patch is not optimal. I'm sure it can be improved a lot. For
example, we could teach the instruction selector to not select lddw/stdw
instructions so that the weird pointer adjustments are not necessary.
But for now I've focused just on correctness, not on code quality.

Updates: https://github.com/llvm/llvm-project/issues/53459

Differential Revision: https://reviews.llvm.org/D131867

[AVR] Do not use R0/R1 on avrtiny

2022-11-28T17:05:55+00:00

This patch makes sure the compiler uses R16/R17 on avrtiny (attiny10
etc) instead of R0/R1.

Some notes:

  * For the NEGW and ROLB instructions, it adds an explicit zero
    register. This is necessary because the zero register is different
    on avrtiny (and InstrInfo Uses lines need a fixed register).
  * Not entirely sure about putting all tests in features/avr-tiny.ll,
    but it doesn't seem like the "target-cpu"="attiny10" attribute
    works.

Updates: https://github.com/llvm/llvm-project/issues/53459

Differential Revision: https://reviews.llvm.org/D138582