llvm-project.git/llvm/test/CodeGen/ARM/div.ll, branch users/nico/python-2

[ARM] Add additional targets to divide tests.

2022-10-17T15:51:17+00:00

The main motivation for these additional targets is to cover the
differences in the instructions available between Thumb2 and Thumb1.

Ths shows up in these test due to the lack of the following in
Thumb1:
- Mulitply and Subtract instruction (mls) - used when calculating
  a remainder.
- Unsigned Muliple Long instruction (umull) - used in certain
  cases when optimising division with a constant.

Differential Revision: https://reviews.llvm.org/D135875

[LegalizeTypes] Improve splitting for urem/udiv by constant for some constants.

2022-09-12T17:34:52+00:00

For remainder:
If (1 << (Bitwidth / 2)) % Divisor == 1, we can add the high and low halves
together and use a (Bitwidth / 2) urem. If (BitWidth /2) is a legal integer
type, this urem will be expand by DAGCombiner using multiply by magic
constant. We do have to take into account that adding high and low
together can produce a carry, making it a (BitWidth / 2)+1 bit number.
So we need to also add back in the carry from the first addition.

For division:
We can use the above trick to compute the remainder, subtract that
remainder from the dividend, then multiply by the multiplicative
inverse of the Divisor modulo (1 << BitWidth).

This is based on the section "Remainder by Summing Digits" in
Hacker's delight.

The remainder trick is similar to a trick you may have learned for
determining if a decimal number is divisible by 3. You can add all the
digits together and see if the sum is divisible by 3. If you're not sure
if the sum is divisible by 3, you can add its digits together. This
can be repeated until you have a single decimal digit. If that digit
is 3, 6, or 9, then the original number is divisible by 3. This works
because 10 % 3 == 1.

gcc already does this same trick. There are additional tricks gcc
does urem as well as srem, udiv, and sdiv that I plan to add in
future patches.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D130862

[ARM] Add support for armv7ve triple in llvm (PR31358).

2017-02-09T23:29:14+00:00

Gcc supports target armv7ve which is armv7-a with virtualization
extensions. This change adds support for this in llvm for gcc
compatibility.

Also remove redundant FeatureHWDiv, FeatureHWDivARM for a few models as
this is specified automatically by FeatureVirtualization.

Patch by Manoj Gupta.

Differential Revision: https://reviews.llvm.org/D29472

llvm-svn: 294661

[ARM] Use AEABI helpers for i64 div and rem

2015-08-24T09:17:18+00:00

Differential Revision: http://reviews.llvm.org/D12232

llvm-svn: 245830

[ARM] support for Cortex-R4/R4F

2015-04-09T14:07:28+00:00

Currently, llvm (backend) doesn't know cortex-r4, even though it is the
default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes
'cortex-r4' is not a recognized processor for this target' by llvm.
This patch adds support for cortex-r4 and, very closely related, r4f.

llvm-svn: 234486

Cortex-R5 can issue Thumb2 integer division instructions.

2013-06-04T22:52:09+00:00

llvm-svn: 183275

Add LLVM support for Swift.

2012-09-29T21:43:49+00:00

llvm-svn: 164899

These tests are looking for library function names that

2010-11-17T21:57:32+00:00

appear to differ on Linux.  Try to make them pass on Linux.
Would be good for a Linux person to review this.

llvm-svn: 119572

Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

2010-08-11T07:17:46+00:00

llvm-svn: 110798

fix copy/paste oops.

2010-05-05T21:07:46+00:00

llvm-svn: 103122