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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU, branch users/nico/python-2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>[PHIElimination] Revert #131837 #146320 #146337 (#146850)</title>
<updated>2025-07-03T11:48:08+00:00</updated>
<author>
<name>Guy David</name>
<email>49722543+guy-david@users.noreply.github.com</email>
</author>
<published>2025-07-03T11:48:08+00:00</published>
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<id>76274eb2b3439aac6991c6b505248e00627e5693</id>
<content type='text'>
Reverting because mis-compiles:
- https://github.com/llvm/llvm-project/pull/131837
- https://github.com/llvm/llvm-project/pull/146320
- https://github.com/llvm/llvm-project/pull/146337</content>
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<pre>
Reverting because mis-compiles:
- https://github.com/llvm/llvm-project/pull/131837
- https://github.com/llvm/llvm-project/pull/146320
- https://github.com/llvm/llvm-project/pull/146337</pre>
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</entry>
<entry>
<title>[InstrEmitter] Use AddOperand in EmitCopyToRegClassNode. (#146637)</title>
<updated>2025-07-02T16:44:54+00:00</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@sifive.com</email>
</author>
<published>2025-07-02T16:44:54+00:00</published>
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<id>b62826cc054cfff75f2b5c83b980f1e12fc25e3a</id>
<content type='text'>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</content>
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<pre>
This is alternative to #145965 that allows RegisterSDNode to be handled
without making a special case.</pre>
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</content>
</entry>
<entry>
<title>[GlobalISel] Allow expansion of urem by constant in prelegalizer (#145914)</title>
<updated>2025-07-02T12:46:36+00:00</updated>
<author>
<name>jyli0116</name>
<email>yu.li@arm.com</email>
</author>
<published>2025-07-02T12:46:36+00:00</published>
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<id>9c0743fbc5ba38ae5f66444d144d314326dc8468</id>
<content type='text'>
This patch allows urem by a constant to be expanded more efficiently to
avoid the need for expensive udiv instructions. This is part of the
resolution to issue #118090</content>
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<pre>
This patch allows urem by a constant to be expanded more efficiently to
avoid the need for expensive udiv instructions. This is part of the
resolution to issue #118090</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Add a debug option `-amdgpu-snop-padding` for `GCNHazardRecognizer` (#146587)</title>
<updated>2025-07-02T12:16:38+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-02T12:16:38+00:00</published>
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<id>c0e9084b1ce1a93fd8c2a650e48b3e11d831b649</id>
<content type='text'>
This can help to identify if there is potential hazards.

Co-authored-by: Byrnes, Jeffrey &lt;Jeffrey.Byrnes@amd.com&gt;</content>
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<pre>
This can help to identify if there is potential hazards.

Co-authored-by: Byrnes, Jeffrey &lt;Jeffrey.Byrnes@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[DAG] visitFREEZE - always allow freezing multiple operands (#145939)</title>
<updated>2025-07-02T10:28:37+00:00</updated>
<author>
<name>Simon Pilgrim</name>
<email>llvm-dev@redking.me.uk</email>
</author>
<published>2025-07-02T10:28:37+00:00</published>
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<id>38200e94f1428b586dc1778133120541e65c20b5</id>
<content type='text'>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</content>
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<pre>
Always try to fold freeze(op(....)) -&gt; op(freeze(),freeze(),freeze(),...).

This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots.

I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe.

Hopefully this will help some of the regression issues in #143102 etc.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)</title>
<updated>2025-07-01T18:08:49+00:00</updated>
<author>
<name>Changpeng Fang</name>
<email>changpeng.fang@amd.com</email>
</author>
<published>2025-07-01T18:08:49+00:00</published>
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<id>5035d20dcbcea1edced779148ac69b84d3c97577</id>
<content type='text'>
These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</content>
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<pre>
These two instructions are supported by gfx1250. We define the
instructions and implement the corresponding intrinsic and builtin.

Co-authored-by: Stanislav Mekhanoshin &lt;Stanislav.Mekhanoshin@amd.com&gt;</pre>
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</entry>
<entry>
<title>[AMDGPU][SIInsertWaitCnts] skip meta instructions early  (#145720)</title>
<updated>2025-07-01T16:32:48+00:00</updated>
<author>
<name>Sameer Sahasrabuddhe</name>
<email>sameer.sahasrabuddhe@amd.com</email>
</author>
<published>2025-07-01T16:32:48+00:00</published>
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<id>a34a02481246482a490c320afb7375ec24cb634e</id>
<content type='text'>
When iterating over a block, meta instructions have no effect on wait counts,
but their presence drops the reference to earlier waitcnt instructions before
they are processed. This results in spurious wait counts, which do not affect
correctness, but are also not required in the resulting program. Skipping meta
instructions as soon as they are seen cleans this up.</content>
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<pre>
When iterating over a block, meta instructions have no effect on wait counts,
but their presence drops the reference to earlier waitcnt instructions before
they are processed. This results in spurious wait counts, which do not affect
correctness, but are also not required in the resulting program. Skipping meta
instructions as soon as they are seen cleans this up.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Fix wrong reverse operations for `v_cmpx_le_u32` (#146398)</title>
<updated>2025-07-01T15:48:08+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-01T15:48:08+00:00</published>
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<id>4dab0b23006017f6bbb3d7c6688f31d14625f86e</id>
<content type='text'>
Fixes: SWDEV-538616</content>
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<pre>
Fixes: SWDEV-538616</pre>
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</entry>
<entry>
<title>[NFC][AMDGPU] Pre-commit a test case that shows wrong reverse operation is used for V_CMPX_LE_U32 (#146527)</title>
<updated>2025-07-01T13:57:04+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-01T13:57:04+00:00</published>
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<id>bab9d4c2d78ad0ee45889be66e006867ddd0bcef</id>
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</pre>
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<entry>
<title>[NFC][AMDGPU] Auto generate check lines for some test cases (#146400)</title>
<updated>2025-07-01T13:25:08+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-01T13:25:08+00:00</published>
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<id>3355cca9380e6e72e5139c6407de7132478635c3</id>
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