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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)"</title>
<updated>2025-11-23T05:17:45+00:00</updated>
<author>
<name>Aiden Grossman</name>
<email>aidengrossman@google.com</email>
</author>
<published>2025-11-23T05:17:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=d5f3ab8ec97786476a077b0c8e35c7c337dfddf2'/>
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<content type='text'>
This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.

This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.
</content>
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<pre>
This reverts commit 0859ac5866a0228f5607dd329f83f4a9622dedcc.

This caused a couple test failures, likely due to a mid-air collision.
Reverting for now to get the tree back to green and allow the original
author to run UTC/friends and verify the output.
</pre>
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</content>
</entry>
<entry>
<title>[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)</title>
<updated>2025-11-23T02:11:24+00:00</updated>
<author>
<name>hstk30-hw</name>
<email>hanwei62@huawei.com</email>
</author>
<published>2025-11-23T02:11:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=0859ac5866a0228f5607dd329f83f4a9622dedcc'/>
<id>0859ac5866a0228f5607dd329f83f4a9622dedcc</id>
<content type='text'>
This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.</content>
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<pre>
This maybe a bug which is introduced by commit
6749ae36b4a33769e7a77cf812d7cd0a908ae3b9, and has been present ever
since.
In this case, `OtherReg` always overlaps with `DstReg` cause they from
the `Copy` all.</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Add baseline test for split/widen invariant loads (#168913)</title>
<updated>2025-11-21T18:53:14+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-21T18:53:14+00:00</published>
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<id>c6876603e9870fd16252f7796871b1a797a10bf1</id>
<content type='text'>
This works fine on main, but broke after a future patch.</content>
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This works fine on main, but broke after a future patch.</pre>
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</entry>
<entry>
<title>Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE." (#169068)</title>
<updated>2025-11-21T17:52:08+00:00</updated>
<author>
<name>Nathan Corbyn</name>
<email>n_corbyn@apple.com</email>
</author>
<published>2025-11-21T17:52:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=4511c355c35153c6b8f5fd3d0b75f77c126fe8e6'/>
<id>4511c355c35153c6b8f5fd3d0b75f77c126fe8e6</id>
<content type='text'>
PR causes build failures with expensive checks enabled

Reverts llvm/llvm-project#168546</content>
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<pre>
PR causes build failures with expensive checks enabled

Reverts llvm/llvm-project#168546</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)</title>
<updated>2025-11-21T15:17:55+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-11-21T15:17:55+00:00</published>
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<id>0b6db777ba9821bc17b969ddf6fefee54519c4f4</id>
<content type='text'>
Fix a problem exposed by #166483 using AV classes in more places.
`isVectorRegister` only accepts registers of VGPR or AGPR classes.
`hasVectorRegisters` additionally accepts the combined AV classes.

Fixes: #168761</content>
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<pre>
Fix a problem exposed by #166483 using AV classes in more places.
`isVectorRegister` only accepts registers of VGPR or AGPR classes.
`hasVectorRegisters` additionally accepts the combined AV classes.

Fixes: #168761</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Stop implementing shouldCoalesce (#168988)</title>
<updated>2025-11-21T15:10:35+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-21T15:10:35+00:00</published>
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<id>bc323b609bd54747b8acda45d91a19f7a343a91b</id>
<content type='text'>
Use the default, which freely coalesces anything it can.
This mostly shows improvements, with a handful of regressions.
The main concern would be if introducing wider registers is more
likely to push the register usage up to the next occupancy tier.</content>
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<pre>
Use the default, which freely coalesces anything it can.
This mostly shows improvements, with a handful of regressions.
The main concern would be if introducing wider registers is more
likely to push the register usage up to the next occupancy tier.</pre>
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</content>
</entry>
<entry>
<title>Fix test from #168609 (#169041)</title>
<updated>2025-11-21T14:24:58+00:00</updated>
<author>
<name>Walter Lee</name>
<email>49250218+googlewalt@users.noreply.github.com</email>
</author>
<published>2025-11-21T14:24:58+00:00</published>
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<id>2a3e745eaa75047e368024ad437950fa239a4aeb</id>
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<pre>
</pre>
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</entry>
<entry>
<title>[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)</title>
<updated>2025-11-21T14:12:17+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>christudasan.devadasan@amd.com</email>
</author>
<published>2025-11-21T14:12:17+00:00</published>
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<id>a2dc4e02e7ba77ddcb0afca0304535d8f142c98b</id>
<content type='text'>
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.</content>
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<pre>
This patch enables the multi-group xnack replay mode by
configuring the hardware MODE register at kernel entry.
This aligns the hardware behavior with the compiler's
existing multi-group s_wait_xcnt insertion logic.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Convert constant-address-space-32bit test to generated checks (#168975)</title>
<updated>2025-11-21T00:45:31+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-11-21T00:45:31+00:00</published>
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<id>3954df93384f10de2ec35501650120949972fbb1</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)</title>
<updated>2025-11-21T00:25:47+00:00</updated>
<author>
<name>Nicolai Hähnle</name>
<email>nicolai.haehnle@amd.com</email>
</author>
<published>2025-11-21T00:25:47+00:00</published>
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<id>ac55d7859fc53d9ca8444a29a93fc45d16ecb26a</id>
<content type='text'>
We previously got a duplicate implicit $exec operand. It didn't really
hurt anything (other than being a slight drag on compile-time
performance). Still, let's keep things clean.</content>
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<pre>
We previously got a duplicate implicit $exec operand. It didn't really
hurt anything (other than being a slight drag on compile-time
performance). Still, let's keep things clean.</pre>
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</content>
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