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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll, branch users/mingmingl-llvm/samplefdo-profile-format</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU] Remove most uses of /dev/null in tests (#156630)</title>
<updated>2025-09-03T15:39:29+00:00</updated>
<author>
<name>Jay Foad</name>
<email>jay.foad@amd.com</email>
</author>
<published>2025-09-03T15:39:29+00:00</published>
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<id>fee17b3a96c29ddef59103bd7c02568f748e37ab</id>
<content type='text'>
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.</pre>
</div>
</content>
</entry>
<entry>
<title>[NFC][FIX] Add `-verify-machineinstrs=0` explicitly to some test files</title>
<updated>2025-07-23T23:12:46+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-23T23:11:12+00:00</published>
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<id>7ae371548f05a94f933db691424b662515afc5a7</id>
<content type='text'>
They had it before but that was removed in #150024. They need to disable the check explicitly to pass expensive checks.
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
They had it before but that was removed in #150024. They need to disable the check explicitly to pass expensive checks.
</pre>
</div>
</content>
</entry>
<entry>
<title>[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMDGPU/*.ll` (#150024)</title>
<updated>2025-07-23T17:42:46+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-23T17:42:46+00:00</published>
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<id>fc0653f31c2a153eaa87f7fe87bd5f1090c4c8ba</id>
<content type='text'>
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)</title>
<updated>2025-06-27T12:05:03+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-27T12:05:03+00:00</published>
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<id>c8ea114741cecf9c812b5e90eaa28919328df650</id>
<content type='text'>
In gfx90a-gfx950, it's possible to emit MFMAs which use AGPRs or VGPRs
for vdst and src2. We do not want to do use the AGPR form, unless
required by register pressure as it requires cross bank register
copies from most other instructions. Currently we select the AGPR
or VGPR version depending on a crude heuristic for whether it's possible
AGPRs will be required. We really need the register allocation to
be complete to make a good decision, which is what this pass is for.
    
This adds the pass, but does not yet remove the selection patterns
for AGPRs. This is a WIP, and NFC-ish. It should be a no-op on any
currently selected code. It also does not yet trigger on the real
examples of interest, which require handling batches of MFMAs at
once.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In gfx90a-gfx950, it's possible to emit MFMAs which use AGPRs or VGPRs
for vdst and src2. We do not want to do use the AGPR form, unless
required by register pressure as it requires cross bank register
copies from most other instructions. Currently we select the AGPR
or VGPR version depending on a crude heuristic for whether it's possible
AGPRs will be required. We really need the register allocation to
be complete to make a good decision, which is what this pass is for.
    
This adds the pass, but does not yet remove the selection patterns
for AGPRs. This is a WIP, and NFC-ish. It should be a no-op on any
currently selected code. It also does not yet trigger on the real
examples of interest, which require handling batches of MFMAs at
once.</pre>
</div>
</content>
</entry>
<entry>
<title>AMDGPU: Use reportFatalUsageError for regalloc flag error (#145198)</title>
<updated>2025-06-22T13:41:05+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2025-06-22T13:41:05+00:00</published>
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<id>96493c514efad52c9fce6db3b0abebf0e61ae93a</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
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</content>
</entry>
<entry>
<title>Revert "[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)"</title>
<updated>2024-12-14T03:47:53+00:00</updated>
<author>
<name>Kirill Stoimenov</name>
<email>kstoimenov@google.com</email>
</author>
<published>2024-12-13T23:36:45+00:00</published>
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<id>e821f642fdc75922b1a020447485acccf3e7fa92</id>
<content type='text'>
Causes bot failure: https://lab.llvm.org/buildbot/#/builders/55/builds/4246/steps/11/logs/stdio

This reverts commit 7a648554f886fbc043c4f3f58ca88f6c4535f2cf.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Causes bot failure: https://lab.llvm.org/buildbot/#/builders/55/builds/4246/steps/11/logs/stdio

This reverts commit 7a648554f886fbc043c4f3f58ca88f6c4535f2cf.
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][CodeGen] Do not backtrace invalid -regalloc param (#119687)</title>
<updated>2024-12-13T06:28:53+00:00</updated>
<author>
<name>Akshat Oke</name>
<email>Akshat.Oke@amd.com</email>
</author>
<published>2024-12-13T06:28:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=7a648554f886fbc043c4f3f58ca88f6c4535f2cf'/>
<id>7a648554f886fbc043c4f3f58ca88f6c4535f2cf</id>
<content type='text'>
No need to generate a stack trace and a GitHub issue prompt on a wrongly
set regalloc option.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
No need to generate a stack trace and a GitHub issue prompt on a wrongly
set regalloc option.</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply "[AMDGPU]Optimize SGPR spills (#93668)"</title>
<updated>2024-10-03T09:47:15+00:00</updated>
<author>
<name>vikashgu</name>
<email>Vikash.Gupta@amd.com</email>
</author>
<published>2024-10-03T09:30:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=870bdc6ea7d98538a2ac80b85d97b7dd1e5ad42d'/>
<id>870bdc6ea7d98538a2ac80b85d97b7dd1e5ad42d</id>
<content type='text'>
This reverts commit c2fc7f75f67039bb1ed577bc0edbd699a850cd9d. As the
dependent patch about split vgpr regalloc pipeline solved the issue(#96353).
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit c2fc7f75f67039bb1ed577bc0edbd699a850cd9d. As the
dependent patch about split vgpr regalloc pipeline solved the issue(#96353).
</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU] Split vgpr regalloc pipeline (#93526)</title>
<updated>2024-09-30T14:25:42+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>christudasan.devadasan@amd.com</email>
</author>
<published>2024-09-30T14:25:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ac0f64f06d67a93817ccd9a3c529ad40920115c9'/>
<id>ac0f64f06d67a93817ccd9a3c529ad40920115c9</id>
<content type='text'>
Allocating wwm-registers and per-thread VGPR operands
together imposes many challenges in the way the
registers are reused during allocation. There are
times when regalloc reuses the registers of regular
VGPRs operations for wwm-operations in a small range
leading to unwantedly clobbering their inactive lanes
causing correctness issues that are hard to trace.

This patch splits the VGPR allocation pipeline further
to allocate wwm-registers first and the regular VGPR
operands in a separate pipeline. The splitting would
ensure that the physical registers used for wwm
allocations won't take part in the next allocation
pipeline to avoid any such clobbering.</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allocating wwm-registers and per-thread VGPR operands
together imposes many challenges in the way the
registers are reused during allocation. There are
times when regalloc reuses the registers of regular
VGPRs operations for wwm-operations in a small range
leading to unwantedly clobbering their inactive lanes
causing correctness issues that are hard to trace.

This patch splits the VGPR allocation pipeline further
to allocate wwm-registers first and the regular VGPR
operands in a separate pipeline. The splitting would
ensure that the physical registers used for wwm
allocations won't take part in the next allocation
pipeline to avoid any such clobbering.</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "[AMDGPU]Optimize SGPR spills (#93668)"</title>
<updated>2024-06-24T07:06:36+00:00</updated>
<author>
<name>vg0204</name>
<email>Vikash.Gupta@amd.com</email>
</author>
<published>2024-06-24T06:36:29+00:00</published>
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<id>c2fc7f75f67039bb1ed577bc0edbd699a850cd9d</id>
<content type='text'>
This reverts commit 4b9112e88a998ce620e4683548f2afd17cc5fe95. A separate
issue(#96353) describing it has been opened to further keep its track.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 4b9112e88a998ce620e4683548f2afd17cc5fe95. A separate
issue(#96353) describing it has been opened to further keep its track.
</pre>
</div>
</content>
</entry>
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