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<title>llvm-project.git/llvm/test/CodeGen/AMDGPU/rotr.ll, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>[AMDGPU][CodeGen][True16] Track waitcnt as vgpr32 instead of vgpr16 for D16 Instructions in GFX11 (#157795)</title>
<updated>2025-09-17T14:09:06+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-09-17T14:09:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=2b2b580c8d4560e724cca7ca856ce7171c3a4628'/>
<id>2b2b580c8d4560e724cca7ca856ce7171c3a4628</id>
<content type='text'>
It seems the VMEM access on hi/lo half could interfere the other half.
Track waitcnt of vgpr32 instead of vgpr16 for 16bit reg in GFX11.

---------

Co-authored-by: Joe Nash &lt;joseph.nash@amd.com&gt;</content>
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<pre>
It seems the VMEM access on hi/lo half could interfere the other half.
Track waitcnt of vgpr32 instead of vgpr16 for 16bit reg in GFX11.

---------

Co-authored-by: Joe Nash &lt;joseph.nash@amd.com&gt;</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (#140694)</title>
<updated>2025-09-11T12:32:44+00:00</updated>
<author>
<name>Chris Jackson</name>
<email>chris.jackson@amd.com</email>
</author>
<published>2025-09-11T12:32:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=5e6564b0989879f8699b476b9ca482653dc0769b'/>
<id>5e6564b0989879f8699b476b9ca482653dc0769b</id>
<content type='text'>
- Enable s_or_b64/s_and_b64/s_xor_b64 for v2i32. Add various additional
combines to make use of these newly legalised instructions.
- Update several tests and separate legacy r600 tests where necessary.</content>
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<pre>
- Enable s_or_b64/s_and_b64/s_xor_b64 for v2i32. Add various additional
combines to make use of these newly legalised instructions.
- Update several tests and separate legacy r600 tests where necessary.</pre>
</div>
</content>
</entry>
<entry>
<title>[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMDGPU/*.ll` (#150024)</title>
<updated>2025-07-23T17:42:46+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2025-07-23T17:42:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=fc0653f31c2a153eaa87f7fe87bd5f1090c4c8ba'/>
<id>fc0653f31c2a153eaa87f7fe87bd5f1090c4c8ba</id>
<content type='text'>
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.</content>
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<pre>
Recent upstream trends have moved away from explicitly using `-verify-machineinstrs`, as it's already covered by the expensive checks. This PR removes almost all `-verify-machineinstrs` from tests in `llvm/test/CodeGen/AMDGPU/*.ll`, leaving only those tests where its removal currently causes failures.</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078)</title>
<updated>2025-04-23T17:06:52+00:00</updated>
<author>
<name>Brox Chen</name>
<email>guochen2@amd.com</email>
</author>
<published>2025-04-23T17:06:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6dbc01e8015816e904687c03f0ea8afac817781d'/>
<id>6dbc01e8015816e904687c03f0ea8afac817781d</id>
<content type='text'>
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.</content>
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<pre>
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.</pre>
</div>
</content>
</entry>
<entry>
<title>Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"</title>
<updated>2024-11-09T01:21:16+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-11-09T01:21:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=6548b6354d1d990e1c98736f5e7c3de876bedc8e'/>
<id>6548b6354d1d990e1c98736f5e7c3de876bedc8e</id>
<content type='text'>
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
</content>
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<pre>
This reverts commit ca33649abe5fad93c57afef54e43ed9b3249cd86.
</pre>
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</entry>
<entry>
<title>Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"</title>
<updated>2024-11-08T21:36:35+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-11-08T21:36:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=ca33649abe5fad93c57afef54e43ed9b3249cd86'/>
<id>ca33649abe5fad93c57afef54e43ed9b3249cd86</id>
<content type='text'>
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
</content>
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<pre>
This reverts commit e215a1e27d84adad2635a52393621eb4fa439dc9 as it broke both
hip and openmp buildbots.
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)</title>
<updated>2024-11-08T18:05:35+00:00</updated>
<author>
<name>Shilei Tian</name>
<email>i@tianshilei.me</email>
</author>
<published>2024-11-08T18:05:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=e215a1e27d84adad2635a52393621eb4fa439dc9'/>
<id>e215a1e27d84adad2635a52393621eb4fa439dc9</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)</title>
<updated>2024-10-21T16:39:52+00:00</updated>
<author>
<name>Stanislav Mekhanoshin</name>
<email>rampitec@users.noreply.github.com</email>
</author>
<published>2024-10-21T16:39:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=3277c7cd28154e33637a168acb26cea7ac1f7fff'/>
<id>3277c7cd28154e33637a168acb26cea7ac1f7fff</id>
<content type='text'>
MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.</content>
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<pre>
MSG_DEALLOC_VGPRS slows down very small waveslot limited kernels. It's
been identified this message is only really needed for VGPR limited
kernels. A kernel becomes VGPR limited if a total number of VGPRs per
SIMD / number of used VGPRs is more than a number of wave slots.</pre>
</div>
</content>
</entry>
<entry>
<title>[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)</title>
<updated>2024-07-23T08:20:42+00:00</updated>
<author>
<name>Christudasan Devadasan</name>
<email>christudasan.devadasan@amd.com</email>
</author>
<published>2024-07-23T08:20:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=a1d7da05d0e8db4690d605e0c767f30e7891ceb2'/>
<id>a1d7da05d0e8db4690d605e0c767f30e7891ceb2</id>
<content type='text'>
Consider the constrained multi-dword loads while merging
individual loads to a single multi-dword load.</content>
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<pre>
Consider the constrained multi-dword loads while merging
individual loads to a single multi-dword load.</pre>
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</content>
</entry>
<entry>
<title>Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)</title>
<updated>2024-07-15T07:51:44+00:00</updated>
<author>
<name>Matt Arsenault</name>
<email>Matthew.Arsenault@amd.com</email>
</author>
<published>2024-07-15T05:59:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.belthelziquor.com/llvm-project.git/commit/?id=b1bcb7ca460fcd317bbc8309e14c8761bf8394e0'/>
<id>b1bcb7ca460fcd317bbc8309e14c8761bf8394e0</id>
<content type='text'>
This reverts commit adaff46d087799072438dd744b038e6fd50a2d78.

Drop the -O3 checks from default-attributes.hip. I don't know why they
are different on some bots but reverting this is far too disruptive.
</content>
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<pre>
This reverts commit adaff46d087799072438dd744b038e6fd50a2d78.

Drop the -O3 checks from default-attributes.hip. I don't know why they
are different on some bots but reverting this is far too disruptive.
</pre>
</div>
</content>
</entry>
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