llvm-project.git/llvm/test/CodeGen/AMDGPU/ret.ll, branch users/nico/python-2

AMDGPU: Replace some float undef test uses with poison (#131090)

2025-03-13T13:07:48+00:00

AMDGPU: Replace undef with poison in tests using insertvalue (#130895)

2025-03-12T09:11:11+00:00

perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'

[AMDGPU,test] Change llc -march= to -mtriple= (#75982)

2024-01-17T05:54:58+00:00

Similar to 806761a7629df268c8aed49657aeccffa6bca449.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```

[AMDGPU] Convert some tests to opaque pointers (NFC)

2022-12-19T11:41:13+00:00

[AMDGPU] Merge GlobalISel tests into SelectionDAG tests. NFC.

2022-11-07T17:39:51+00:00

Remove GlobalISel test files that only contained RUN lines running the
code from the SelectionDAG version of the same test.

Differential Revision: https://reviews.llvm.org/D137533

AMDGPU/GlobalISel: Handle most function return types

2019-07-26T02:36:05+00:00

handleAssignments gives up pretty easily on structs, and i8 values for
some reason. The other case that doesn't work is when an implicit sret
needs to be inserted if the return size exceeds the number of return
registers.

llvm-svn: 367082

AMDGPU: Drop remnants of byval support for shaders

2019-07-12T20:12:17+00:00

Before 2018, mesa used to use byval interchangably with inreg, which
didn't really make sense. Fix tests still using it to avoid breaking
in a future commit.

llvm-svn: 365953

Bias physical register immediate assignments

2018-11-14T21:11:53+00:00

The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.

This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out-of-registers
assertion (PR39391).

Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.

Reviewers: MatzeB, qcolombet, myatsina, pcc

Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya,
  javed.absar, arphaman, jfb, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D54218

llvm-svn: 346894

AMDGPU: Fix code size for return_to_epilog pseudo

2018-07-27T09:15:03+00:00

llvm-svn: 338113

Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"

2018-02-27T16:59:10+00:00

Re-enable commit r323991 now that r325931 has been committed to make
MachineOperand::isRenamable() check more conservative w.r.t. code
changes and opt-in on a per-target basis.

llvm-svn: 326208